Sierra Design Automation, in Collaboration With Mentor Graphics, Enables Lithography-Driven Closure for 65nm/45nm Designs

Business Wire, July 17, 2006

SANTA CLARA, Calif. -- Lithography and Variation-Driven IC Implementation System Helps Customers Achieve Faster Design Closure and Higher Yields

Sierra Design Automation, Inc., the Design for Variability technology leader, today announced it is collaborating with Mentor Graphics(R) (Nasdaq:MENT), a world leader in electronic hardware and software design solutions, to address the critical issue of process and lithography variations in an IC implementation design flow targeted at 65nm and 45nm designs.

The Problem

The advent of 65nm and 45nm process nodes has resulted in three significant design and manufacturing challenges:

--Process and Design related Timing Variations (a.k.a Design for Variability or multi-mode multi-corner)

--Lithography Variations

--Very large design sizes

At 65nm and below, manufacturing faults such as "bridging" and "pinching" need to be detected and fixed much earlier in the design flow. Since manufacturing-related layout modifications increasingly involve local re-routing, this can significantly impact the circuit performance over all the different process corners and design modes. The Sierra/Mentor collaborative effort is focused on delivering an IC implementation flow with the highest capacity, industry-leading Design for Variability and the industry's premier Litho-Friendly Design environment to mutual customers of the two companies. The companies also announced that the new solution is currently being validated on multiple designs at mutual customer sites.

For the 65nm/45nm process nodes, there is an urgent need for a solution that bridges the gap between OPC/RET and IC design -- specifically the timing impact of manufacturing-related layout modifications. Design teams are actively looking to address process and litho variations early in the design cycle.

Overview of Calibre(R) LFD(TM) and Sierra Olympus-SoC(TM)

Calibre LFD enables designers to verify how a layout will print under a particular lithographic process window and is rapidly gaining adoption as the premier design-based litho sign-off environment. The LFD kit includes energy, dose and mask bias considerations, RET recipes, process models, and the parameterizable rules to be checked, all presented in a common results database. Calibre LFD is being actively adopted by many design and manufacturing houses.

Sierra Olympus-SoC is the only IC implementation solution designed to comprehensively analyze and optimize for variability through all the steps of the design flow. With the highest capacity implementation architecture, native sign-off quality timer with patented virtual timing graph technology, and best-in-class physical implementation engines, designers can account for design, process and lithography variation throughout the IC design flow. Sierra's next-generation detailed routing architecture embeds sign-off variation-aware timing, optimization, and litho-modeling to address OPC/RET effects early in the design cycle to ensure faster timing closure for complex process rules of 65nm and below.

The Collaborative Effort

Sierra Olympus-SoC interacts with Calibre LFD to obtain the database of lithography hot-spots and litho-unfriendly structures and then changes the design layout to fix these errors without affecting the overall timing performance and OCV-related hold violations. The Olympus-SoC engines can modify the layout to fix these litho errors with customized routing techniques. The collaborative effort also focuses on defining new types of litho-friendly design rules that will be used by Sierra IC implementation flow to produce inherently more litho-friendly designs. This flow will enable faster design closure in addition to delivering higher yields.

"Calibre LFD enables designers to make trade-off decisions on how to create a design that is more robust and less sensitive to the lithographic process windows," said Joe Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics. "This became important at the 90 nanometer technology node, and is crucial at the 65 and 45 nanometer nodes, where process variations can greatly influence silicon results. We are excited to work with Sierra Design Automation and its variability-aware implementation system because it is an ideal platform to take advantage of this analysis to make timing-driven layout modification trade-offs at earlier stages of the design flow to dramatically improve layout robustness across process windows."

"Current techniques for litho hot-spot removal make modifications to the layout without taking into consideration critical design metrics such as timing performance and OCV-related hold violations," said Pravin Madhani, CEO and President, Sierra Design Automation, Inc. "Sierra's variability-aware IC implementation system can model the errors identified by the Calibre LFD simulations and can modify the design layout while ensuring timing closure. We believe that our mutual customers will benefit immensely from our collaborative efforts."