Verific Licenses HDL Component Software to ProDesign; Verific's HDL Parsers Enable New ASIC Verification Capabilities For ProDesign's CHIPit High-Speed ASIC Prototyping Systems

Business Wire, March 28, 2006

ALAMEDA, Calif. -- Verific Design Automation today said that it has licensed its hardware description language (HDL) Component Software to ProDesign, a leading supplier of high-speed application specific integrated circuit (ASIC) and system-on-chip (SoC) verification platforms.

Verific's software is being used as the register transfer level (RTL) front end for ProDesign's ASIC prototyping system. ProDesign has integrated Verific's C source code-based parsers, analyzers and elaborators for Verilog and VHDL with the CHIPit(R) ASIC prototyping systems.

"Verific offers an exceptional package that includes production-proven, quality software, along with excellent support and service," says Gunnar Scholl, ProDesign's director of Marketing and Business Development. "We looked no further than Verific when we sought out a front-end development partner. With the integration of Verific's HDL Component Software we could expand the capabilities of our CHIPit systems, especially for the transaction-based verification. This enhanced concept opens new functionalities for pre silicon system and software verification."

Michiel Ligthart, Verific's chief operating officer, remarks: "ProDesign has a compelling story and we're delighted to be part of it. ASIC prototyping is a viable verification strategy, due in large measure to ProDesign's tools."

About ProDesign

The privately held company was founded in 1981 and has over 80 employees, with various facilities for research, design, and sales in Germany, France and the U.S. ProDesign has more than 24 years of experience as a service provider and manufacturer in the electronics industry. The company's products and services include the CHIPit family of High-Speed ASIC Prototyping Systems to validate algorithm performance, verify hardware implementation, and assist in hardware/software co-development and co-verification to reduce the verification time dramatically. For more information about the company's prototyping products, please visit: http://www.prodesign-europe.com.

About Verific Design Automation

Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C source code-based SystemVerilog, Verilog and VHDL front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: http://www.verific.com.

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