Intellitech Announces Support for Xilinx Virtex 4 at-speed SERDES Tests in Its Eclipse IEEE 1149.1/JTAG products

Business Wire, Oct 24, 2006

SANTA CLARA, Calif. -- Intellitech Corporation, www.intellitech.com, the leader in lowering product costs through IEEE 1149.1/JTAG, has announced the support for Xilinx Virtex 4 RocketIO in its at-speed BERT-IP test module for Eclipse. BERT is an acronym for Bit Error Rate Test a well known industry metric in measuring high-speed link quality. The BERT-IP when used with Intellitech's Eclipse JTAG tools is now capable of testing all combinations of Virtex 2 and Virtex 4 RocketIO interconnect at speeds up to six Gigabits per second. The BERT-IP consists of a downloadable bitstream for the FPGA with built-in pattern generators, high speed transceiver controls and pattern receivers that enable the real time detection and display of bit errors. The design engineer can set error limits and other parameters then export the BERT-IP at-speed tests for automatic execution at power-up or for in-the-field use through Intellitech's SystemBIST FPGA configuration device. The tests can also be exported for use during production JTAG tests and don't require a fully assembled system in order to be executed. At-speed tests can be performed on single PCBs or high-speed interconnect across multiple PCBs. Intellitech demonstrated the technology today on a customer designed PCB that incorporates several Virtex 4 devices and several 3.125G/s links at the International Test Conference exhibition hall.

The technology is particularly important today as SERDES is not just used in high performance networks, but is used just to reduce the routing complexity of IC to IC interconnect. The BERT-IP technology enables customers to test these multi-gigabit SERDES connections at their rated speed and diagnose common PCB faults that can increase the bit error rate to unacceptable levels or prevent the connections from functioning all together. Intellitech's BERT-IP for Xilinx RocketIO enables testing for a large number of pins that can't be tested with standard IEEE 1149.1/JTAG because there aren't boundary-scan capabilities on those particular FPGA pins. An FPGA with twenty Xilinx MGTs (Multi-Gigabit Transceiver) has two pair of differential I/Os for a total of eighty pins that don't have boundary-scan test on them. The high speed operation of the nets constrains the construction of vias and test points on the PCB making other test techniques such as flying probe or in-circuit test difficult or impractical. The BERT-IP tests replaces software based functional tests which require significantly more resources to develop, may not be re-useable on next generation systems, have poor fault isolation and may not fully exercise the link for all possible faults.

"Clock Jitter, power supply noise, cross talk, heat, poor PCB routing, impedance mismatches and signal reflections are all well known enemies of multi-gigabit SERDES designs", said Bill Tuthill, Intellitech BERT specialist, "software based functional test is good at finding an open link but seldom has the depth to identify random faults induced by these type of phenomena." He continued, "Costs go up linearly in terms of engineering time and overhead in order to get that depth and granularity in a functional SERDES test." "BER tests take a lot of logic, not something you would load into the FPGA with the functional design anyway, so rather than design your own in-house solution, the BERT-IP solution will provide a re-useable drop in FPGA bitstream with software to enable these types of robust tests. The BERT-IP is a plug-n-play module that can be used to quickly get you up and running during prototyping as well as be loaded into the FPGA temporarily at power-up as a built-in test" Tuthill concluded.

The BERT-IP module for Xilinx Virtex 4 and Virtex 2 is available now. The software license has a base price of $2995.00.

Trademarks

SystemBIST and Eclipse are trademarks of Intellitech Corporation. Intellitech is a registered trademark of Intellitech Corporation. RocketIO is a trademark of Xilinx, Inc. Xilinx and Virtex are registered trademarks of Xilinx, Inc.

About Intellitech

Intellitech's TEST-IP(TM)family provides patented infrastructure IP that enables customers to lower the cost of designing, debugging, producing and maintaining electronic systems. Intellitech's proprietary solutions enable customers to build self-testable and in-the-field re-configurable products with the least amount of engineering resources and at the lowest cost. Intellitech lowers production costs by embedding test or enabling concurrent test of electronic assemblies during production test and burn-in. The unified test and configuration approach enables customers to lower manufacturing test costs, provide field adaptable products and retard product obsolescence with field upgrade-able logic.