PLDA Announces Immediate Availablity Of PCIe 2.0 IP Core Supporting New Xilinx Virtex-5 FXT FPGAs

Business Wire, April 9, 2008

PLDA FPGA IP Core is compliant with Revision 2.0 of the PCIe specification

SAN JOSE, Calif. -- PLDA, the industry leader in the high-speed bus IP market, today announced the immediate availability of their PCIe Gen 2 FPGA IP support for the Virtex[R]-5 FXT platform, Xilinx's "ultimate system integration platform". The PLDA PCIe IP Core is 100% compliant with Revision 2.0 of the PCIe specification and supports both x1 and x4 configurations.

Today's announcement highlights the demonstrated leadership of PLDA in PCIe Gen 2 bus interface IP cores. It follows PLDA's announcement and demonstration in May of 2007 of their PCIe Gen 2 for ASIC, displaying the highest speed, functioning PCIe IP core on the market. PLDA is now extending the performance and advantages of its PCIe for ASIC IP core into the newest technology Xilinx FPGAs.

Key features of the PLDA PCIe Gen 2 IP Core for Xilinx include:

* Application layer with up to 8 automated DMA engines

* High performance interface allows up to 16 simultaneous outstanding requests

* Complete support for scatter-gather

* User interface similar to PLDA's EZ DMA IP (DMA Application layer designed to work with the Virtex-5 family's embedded endpoint block)

"The PLDA PCIe 2.0 (5 Gbps) IP core plus built-in PCIe 1.1 blocks in Virtex-5 FXT FPGAs will expedite design and development of PCI Express applications," said Anil Telikepalli, Senior Manager of Solutions Marketing at Xilinx. "As the ultimate system integration platform, the Virtex-5 FXT platform's support of PCI Express 2.0 will enable designers to leverage the capabilities of the new device while lowering total system costs."

The Xilinx Virtex-5 FXT devices are the industry's first FPGAs with embedded PowerPC440 processor blocks, high-speed RocketIO[TM] GTX transceivers and dedicated XtremeDSP[TM] processing capabilities, offering designers high levels of system integration and performance. Each processor, with integrated 32KB instruction and 32KB data caches, delivers up to 1,100 DMIPS at 550 MHz. Tightly coupled to the PowerPC440 blocks is a new, integrated 5x2 cross bar processor interconnect architecture that provides simultaneous access to I/O and memory for high system throughput. For more information on Virtex-5 FXT devices please visit: http://www.xilinx.com.

According to Stephane Hauradou, PLDA's CTO, "PLDA was pleased to receive PCI-SIG certification for our PCIe 2.0 solution during the October 2007 PCI-SIG PlugFest. This was a key validation of our product's integrity and will help enable customers who use the core with Virtex-5 FXT devices," Hauradou added, "In June 2007, PLDA announced the industry's highest-performance PCIe 2.0 IP cores for ASIC and has since garnered several design-wins, demonstrating the readiness of the market for PCIe 2.0."

See a Demonstration of the PLDA PCIe Gen 2 IP Core for FPGA:

PLDA will be demonstrating its PCIe Gen 2 IP for the Virtex-5 FXT FPGAs at the Embedded System Conference (ESC) show in San Jose, CA from April 15th until 17th. For details on the demonstration, please contact PLDA directly at sales@plda.com or visit their booth at ESC in Stand 532.

About PLDA

PLDA designs and sells a wide range of ASIC and FPGA IP solutions including bus controllers and bridges IPs. The company offers complete solutions, including IP cores, hardware, software, consulting services, and comprehensive technical support provided directly by the IP designers.

Founded in 1996 and profitable since its inception, PLDA is privately owned. The company maintains offices in San Jose, California and headquarters in France and has a strong international distribution network. For additional information about PLDA, please visit http://www.plda.com.

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