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Brion Introduces Its Next-Generation Tachyon 2.5 Platform and Tachyon DPT, to Help Chip Makers Break Through 32 Nanometer Barrier for More Powerful Semiconductors

Business Wire, Feb 25, 2008

SANTA CLARA, Calif. -- Brion Technologies, an ASML company, today introduced Tachyon 2.5, a significantly more-powerful version of its flagship Tachyon[TM] Computational Lithography platform. Brion also announced the immediate release of Tachyon DPT, an advanced double patterning (DPT) solution that allows chip makers to meet the low k1 requirements for memory and logic devices at 32 nanometers (nm) and below using advanced lithography systems.

Tachyon 2.5's combination of enhanced system and firmware advancements, together with faster processors, continues to meet the industry's need for greater computational power; supporting the rapid adoption of DPT and other low k1 resolution enhancement technologies. Tachyon 2.5 provides up to 150% (2.5x faster) greater performance than previous Tachyon systems with minimal increase in IT infrastructure costs.

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Tachyon DPT uses Brion's latest double patterning technology to allow advanced chip makers to develop devices down to the 22nm technology node. A production-ready, complete end-to-end solution that is available now, it supports both litho- (litho-etch-litho-etch) and spacer-DPT - two leading double patterning techniques. Tachyon DPT offers full-chip conflict-free pattern split, model-based OPC, model-based stitching compensation, and automatic density balancing.

"Tachyon DPT enables Brion's customers to continue their manufacturing leadership," said Neal Callan, Brion's vice president of product operations. "Tachyon DPT, along with our existing Source-Mask Optimizer (SMO) capabilities, provides a comprehensive 22nm enabling solution for both R&D and production."

Tachyon DPT, a comprehensive double-patterning solution available today with SMO capabilities, enables multiple Brion customers to produce advanced memory and logic geometries.

"Hynix recognizes the industry-leading performance of Brion's Tachyon DPT solution. Double patterning will be part of our low k1 imaging techniques and will be instrumental in our plans to begin producing devices at 32nm and below," said Dong Gyu Yim, Ph.D research fellow, Hynix Research & Development Division.

Tachyon DPT is currently available, and Tachyon 2.5 will be available in June 2008.

About Double Patterning

Double patterning is a semiconductor exposure method that involves splitting dense circuit patterns into two separate, less dense circuit patterns that are then printed individually on a target wafer. The second pattern is printed between the lines of the first pattern, enabling the fabrication of denser patterns than would otherwise be possible. This technique is helping to extend current microlithography technology to future production nodes.

About k1

Lithographers use the "process factor" k1 to express the relative difficulty of a given lithography process. Improvements in lithography system capabilities, photoresist processes, and masks enable lithography at smaller k1 values, which in turn allows chipmakers to produce devices with increasingly smaller features, with minimal sacrifice of process latitude.

About Source-Mask Optimizer (SMO)

Source-Mask Optimizer (SMO) is an ASML proprietary option within Brion's LithoCruiser simulation suite that simultaneously optimizes ASML scanners' illumination shape/settings and the model-based OPC for critical low k1 memory core features. SMO features include: full integration with access to LithoCruiser's on-board ASML scanner specification database, multi-clip optimization with weighting, overlapping process window and mask error enhancement factor as metrics.

About Brion Technologies

Brion Technologies is an ASML company and industry leader in computational lithography for integrated circuits. Brion's Tachyon[TM] platform, an OPC and OPC verification system, enables capabilities that address chip design, photomask making and wafer printing for semiconductor manufacturing. Brion is headquartered in Santa Clara, California. For more information: www.brion.com or www.ASML.com

Business Services Industry

Brion Introduces Its Next-Generation Tachyon 2.5 Platform and Tachyon DPT, to Help Chip Makers Break Through 32 Nanometer Barrier for More Powerful Semiconductors

Business Wire, Feb 25, 2008

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