TSMC Reference Flow 9.0 Covers Apache's Advanced Leakage and System Jitter Analysis

Business Wire, June 10, 2008

Apache's RedHawk and Sentinel Platforms Support TSMC 40nm Process Technology

SAN JOSE, Calif. -- Apache Design Solutions, the technology leader in power, noise, and reliability (PNR) signoff for chip and package designs, today announced that Taiwan Semiconductor Manufacturing Company (TSMC) Reference Flow 9.0 includes Apache's advanced leakage and system-wide jitter analysis solutions for TSMC's 40nm process technology. Specifically, Reference Flow 9.0 will accommodate new Apache innovations for:

* Power noise analysis with RedHawk qualified for transparent half-node design

* Thermal-aware statistical leakage modeling and analysis with RedHawk-ALP

* System jitter analysis including on-chip and high performance Input/Output (I/O) noise with Sentinel-SSO

At advanced process nodes, leakage power dominates total power and the process variation starts to have a significant impact on leakage variation. In order to reduce excessive design margins and optimize performance, a statistical leakage power model for intra-die and inter-die distribution is needed. In addition, leakage is strongly dependent on the operating temperature. RedHawk-ALP enables designers to perform accurate leakage analysis with by providing a model of statistical process variation of leakage power for the full-chip, including the impact of temperature, thus improving design margin and performance.

A high-performance I/O such as DDR is highly susceptible to timing failures due to jitter noise on the I/O interface. System jitter analysis needs to consider both the on-chip noise and I/O noise with the consideration of package/PCB effects. In order to minimize system timing failure risks and improve engineering productivity, a quantitative method for measuring on-chip and I/O jitter is needed. In addition, the impact of dynamic power noise needs to be considered for accurate jitter measurement. Sentinel-SSO delivers the ability to analyze jitter and determine the noise impact on system timing, thus minimizing design failures post tape-out.

"Over the past several years, TSMC has worked with Apache to meet latest deep sub-micron design challenges," said Tom Quan, deputy director, design automation and service marketing at TSMC. "Through Reference Flow 9.0, Apache can provide unique solutions for managing advanced low power and system timing requirements for our latest 40nm process nodes."

"We are pleased with the continued collaboration between TSMC and Apache in delivering methodologies that address the most advanced power, noise, and reliability challenges faced by designers," said Dian Yang, senior vice president of product management at Apache. "Apache's product portfolio benefits our designers by delivering accurate and reliable power signoff solution."

About Apache Design Solutions

Apache delivers the leading power signoff solution adopted by 80% of the top IDM, fabless semiconductor, and foundries and a complete platform for silicon integrity of low-power, high-performance system-on-a-chip (SoC) designs. Apache's innovative platform considers multiple noise sources that impact the design--such as power, signal, package / system IO, substrate, and temperature--and enables designers to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon and/or system. Apache's vendor-neutral solution supports any industry-standard physical design flow and is certified by TSMC and Common Platform Reference Flows. Apache is a global company with R&D centers and direct sales / support offices worldwide. For more information, visit www.apache-da.com.

Apache Design Solutions, NSPICE, RedHawk, PakSi-E, PakSi-TM, PsiWinder, Sahara, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.