Interra Systems to Exhibit Products during Design Automation Conference

Business Wire, June 3, 2008

Announces BIST for MC2, Enhancements to EDA Language Front-Ends

SAN JOSE, Calif. -- Interra Systems, a leading provider of EDA building blocks, methodologies, and services for SoC designers, will exhibit MC2, the Memory Development System and EDA language analyzers during the 45th Design Automation Conference June 9-12 in the Anaheim Convention Center at booth #1937. New products/features include BIST - the Built-In-Self-Test Capability for MC2, major enhancements to its SystemVerilog and VHDL analyzers and a new front-end for UPF/CPF standards for power aware EDA products.

Considering wide spread usage of embedded memories as part of today's SoC, it has become important to provide special purpose test infrastructure for memories. MC2 now generates optimized RTL for Built-In-Self-Test (BIST) that enables execution of test algorithms for better verification and diagnostics environment for created memories. The BIST capability of MC2 includes support for well defined algorithms as well as mechanism for the user to specify their own algorithms.

Major enhancements and improvements to our language front-ends were driven by the active production usage of Cheetah - the Verilog and SystemVerilog analyzer, Jaguar - the VHDL analyzer and Concorde - the front-end synthesis technology by its major EDA customers like Mentor, Cadence, Magma, Eve and several other startups.

In addition, Interra is actively working to add new EDA standards to its portfolio like UPF/CPF. Unified Power Format (UPF) and Common Power Format (CPF) allow users to specify power intent and constraints for EDA tools. Several EDA tools from synthesis, analysis, simulation to place and route are required to adhere to critical power requirements and constraints specific to given SoC. UPF/CPF front-End from Interra Systems helps build these tools quickly with standard compliance.

Visit http://www.interrasystems.com/registration_dac08.php or contact Vijeta Kashyap at (408) 985-2200 x2015 (vijeta@interrasystems.com) to schedule a demo.

MC2, the Memory Development System: MC2 provides a feature rich platform to define memory architecture using a language that is then used for instance creation, characterization, self-test, and validation. Several SoC companies and semiconductor foundries have taken advantage of MC2 capabilities for scaling their memory designs to higher densities, placing memories within their SoC, ASIC or IC designs, and to make their design process more efficient.

Front-End for EDA Tools: Cheetah - the Verilog and SystemVerilog analyzer, Jaguar - the VHDL analyzer as language front-ends and Concorde - the synthesis front-end are used actively by several well known industry tools from major EDA vendors as well as startups. Robust field proven quality, professional support and customization services enable EDA tool developers to reduce time-to-market and development cost. Interra provides the latest support for VHDL standard IEEE 1076, Verilog standard IEEE 1364 and SystemVerilog standard IEEE 1800. Interra also provides analyzers for other EDA standards like Mixed HDL, PSL, SDF, Liberty, SPEF, DSPF, SAIF, VCD, UPF, CPF, GDSII, LEF and DEF.

Test Suites to Validate EDA Tools: Beacon family includes test suites for System Verilog, Verilog 2001, Synthesizable Verilog and VHDL, Verilog/VHDL mixed interface, PSL and HSPICE. Beacon test-suites are used by several companies to ensure compliance, coverage and quality of their tools' support for EDA standards. Beacon offers reduced development costs and time to market for EDA tools.

Digital Media: Digital Media offerings from Interra help media companies and product developers to check the standard compliance and enhance the quality of media products and content. Vega, the family of media Analyzers, provides an efficient debugging point in broadcast media enabling, system integration, and technology development. Baton, the automated content verification system, is a software-only solution for quality control of media content in file-based SD, HD, and mixed workflows.