Cadence Tips System-Level Hat

Electronic News, Jan 10, 2000 by Gale Morrison

After two and a half years of development, Cadence Design Systems Inc. this week is starting general release of its Cierto VCC (Virtual Component Co-Design) design environment.

Cierto VCC, formerly code-named Felix, is a system architect tool that can partition and simulate the system design before implementation level, i.e., before the hardware design language (HDL) or assembler code for software is written. Intricate performance evaluations (with clock cycle and silicon area estimation) can be done and then the design is handed off for implementation level code generation.

The release of Cierto VCC comes at a time when many were starting to count Cadence out of the market for such tools. One electronic design automation (EDA) analyst, who didn't want to be named, said he had suspected there was some kind of problem associated with Cierto due to Cadence's silence on the product.

But Cadence did not spend so much time and untold millions in R&D for nothing. The capabilities in Cierto VCC are above and beyond anything else available, according to Cadence, although competitor CoWare Inc. takes exception to that notion. (CoWare is Synopsys Inc.'s partner in the SystemC C-based design initiative, which competes with Cierto.)

"This is really important and a big step upwards in abstraction," said Frank Schirrmeister, senior technical marketing manager at the System Level Design group (formerly known as the Alba group) of Cadence, San Jose. "What would take 16 seconds in real-time on the system, will take 30 seconds on a PC (with Cierto VCC). At the implementation level, that would take hours, even days."

Taking EDA into New Markets

Cierto furthers the EDA industry's goal of expanding the market it serves. By providing system houses with top-down system tools, EDA takes a bold step away from the heavily segmented market of the 1990s, which was split into silicon design tools and lower rent board-level tools, neither of which had any real knowledge of the system software.

"We geared Cierto VCC at two kinds of users, reflecting the changing work relationship between design teams and system houses," Schirrmeister said. "System houses, like Ericsson and BMW, can articulate their requirements to their semiconductor suppliers. And semiconductor suppliers can present their architectural solutions, how their chipsets would work in the platform."

Philips Semiconductors is using Cierto VCC in concert with its own system design platform, known as Nexperia, said Marinus van Lier, manager of system level design in Philips' Design Technology group.

"This will be a tool to interface with the customer to negotiate the specification," van Lier said.

Philips' first application of the VCC methodology is for the design of a prototype system-on-a-chip (SOC) decoder for digital video broadcast applications that will be completed in June, according to Cadence.

CoWare Draws Distinctions

Competitor CoWare Inc. said the big difference between Cierto VCC and its product, dubbed the N2C design system, is performance evaluation. In terms of performance evaluation, such as clock cycle estimation, Cierto VCC's "technology just isn't there yet," said Pete Hardee, director of product marketing for CoWare.

Gary Smith, principal EDA analyst at the San Jose market research firm Gartner Group/Dataquest, said both companies are barking up the wrong tree.

"CoWare and Cadence don't really compete, although I don't think either one has noticed. CoWare specializes in what I call 'embedded silicon.' It has a great tool for a very specific market and it is becoming a very large market. Cadence is trying to approach a much bigger problem and that is the large, 10 million-gate-plus SOC designs. That means today their targeted market is much smaller as few companies know how to do the really big designs. I'm sure that if Cadence tries to get into the smaller size embedded silicon market, they will lose out to CoWare.

"On the other hand they have a great opportunity, and a big missionary job, ahead of them in the SOC market," he said.

United States Falling Behind?

Smith said the greatest number of Cadence missionaries are needed in the United States, as European firms (as evidenced by the EU consortia participation and customer testimonials) are already on board. This is a point U.S. firms must consider carefully, Smith said.

"Europe is way ahead of the United States in electronic system-level design and therefore hardware/software co-design," he said. "A lot of the new core-based design technology is coming out of Europe. EDA vendors are having a hard time getting U.S. companies' interest.

"The real bad news is that Japan has decided to follow the Europeans, and if the United States doesn't wake up, they will be ahead of us in a few years," Smith said.

The United States may not be awake to this new methodology yet because Cadence was in fact so quiet about it, especially States-side. Schirrmeister said Cadence wanted to prove the technology beyond a reasonable doubt before extolling it.