EDA and IP: A Long Voyage Ahead

Electronic News, Jan 31, 2000 by Gale Morrison

New York -- Everyone knows the slogan: Build chip designs in functional blocks and they will be reusable, while those long, missed-the-market design cycles will melt away, much like the ice and snow on the East Coast last week.

The people aren't buying it. Yet.

"The fairy tale a few years ago was that engineers could pick and choose from this off-the-shelf IP (intellectual property), and their designs would be done, and the clouds would break and the birds would sing," jokes Jim Turley, vice president of marketing at ARC Cores Ltd. in London. "The reality is actually very nasty. It's very tough. It's one of those hidden, nasty truths of the SOC (system-on-a-chip) era."

Only the hardened, select few who are verifying away in the trenches -- or paying heavily for an IP vendor's engineering team to do it for them -- can even see the light at the end of the SOC revolution tunnel.

"If you look at who uses the most IP today, it's the IDMs: TI, Intel, the ASIC guys like LSI or Lucent," said Bill Alexander, product marketing for Avant!, Fremont, Calif. "These people who have developed the expertise, they have allowed their IP to evolve. Intel is a great example of that, with the progression of the x86 architecture.

"Those guys who actually have IP reuse today ... it's in-house. And they don't commercialize it," said Alexander.

So, what are third-party IP vendors doing in the face of the reality of a small customer base?

"IP guys have focused their relationship on the foundries. That is the channel that I believe they've been pursuing and they still continue to pursue. They use the marketing channels of the foundries and the ASIC guys to get their IP into designs," said Alexander.

"Foundries and ASIC are the number one priority for IP vendors. A lot of the foundries will have their own design services that they promote. Clearly, it includes a mixture of tools on many vendors. If the IP vendors developed their core together with TSMC (Taiwan Semiconductor Manufacturing Co.) or LSI Logic, it's through those relationships that we sometimes get involved. The EDA (electronic design automation) vendor comes in through the relationship with foundry or the ASIC house," he added.

The IP vendors though are not wrong in looking to the foundries, because the foundries appear to be opening their wallets, said F. Taylor Scanlon, the president and chief executive officer of Virtual Silicon Technology, an IP library provider.

"Foundries, much like the historical ASIC business, are learning that IP and embedded memories and all kinds of building blocks are the keys to growing their business," said Scanlon. "The thing that's new, the thing that you'll see in the next ten years as different from the last ten years, is that no single vendor can do it all. The foundries recognize that they need programs to (reward financially) and entice customers."

Scanlon makes the point in support of his own company's goals, too. Virtual Silicon said today that its October partnership with UMC (United Microelectronics Corp.) of Taiwan, the world's second largest IC foundry, has brought a full 0.15-micron IP library that is available now, free of charge.

UMC paid Virtual Silicon to develop this proven, engineered IP and Virtual Silicon will market and distribute it. When a UMC customer tapes out, UMC pays Virtual Silicon the royalty for bringing in the foundry business, for helping to fill the fab. It's a workable, shared risk/reward model, Scanlon says.

Still, EDA and IP vendors are struggling enormously with a verification scheme for block-based design, and that's true at the "star IP" houses like MIPS and ARM, and within the "jelly bean IP," library development teams, who work all over the industry on much smaller functions like memory controllers.

"The MIPS people have to actually do the same things that a library vendor has to do. They have to produce 'views' that work at a high-level, the behavioral, the RTL, and the physical-level views ... the job of producing views for a piece of IP is pretty much the same for an IP vendor as for a library guy. They have to produce particular models," said Avant!'s Alexander.

"But besides the views, the extra job that the IP guys have is ensuring that their design can be verified once it's in the system. They are saying, 'How do I verify? How do I ever test this thing?' They need to develop a far more complex model and a strategy for verifying," he added.

"Where the (EDA and IP vendors) can certainly improve is a set of tools that is used to characterize the complex intellectual blocks with models that can be viewed by many tools, and a strategy that enables the user to verify how he would use that IP block in this design," Alexander said. "The pervasive model today is .lib ("dot lib") from Synopsys. But there are other descriptions that one could have, using Verilog and VHDL and even C.

"There should be tools that can produce these views ... that is an area that needs a lot of development, I think. The market isn't that big right now and I don't think people will have a strong drive towards it, but no doubt, moving forward, that is a strategic area in order for IP to be developed fast enough and comprehensively enough," he said.