Block-Based Design Planning

Electronic News, Jan 31, 2000 by Jacob Greidinger

The Road to Failure is Paved with Good Intentions

Attempts at design reuse will falter unless supporting design methodologies change to accommodate them. The larger the design, the greater the imperative for reusable functional blocks and a block-based design implementation.

In particular, RTL cores pose a problem due to the multitude of implementation alternatives, which in turn determine chip-level performance. Designers need early design planning and successive refinement of these cores to add predictability to the design process. By automating this block-based design planning and successive refinement process, designers can quickly and predictably implement RTL cores within the context of the overall chip.

The ability to work easily with different logical and physical hierarchies is an invaluable aid to this process. When combining different cores at the architectural or logical stage, it is natural to think of them as disjointed building blocks that must be melded together to form a working unit.

However, when it comes time to physically lay out the chip, designers can obtain superior results by combining multiple logical units into larger groups that can take advantage of automated layout technology.

Using block-based design techniques, designers of complex ICs and SOCs are able to automatically adjust the hierarchical structure of the design according to the current stage of the process. In both the logical and physical domains, they can work at the level of abstraction that is most natural and will yield the best results.

Enabling Block-Based Design

Our IC Wizard product line was designed with these considerations in mind. During the early stages of design, the architectural designer may create chip-level design plans comprising fifty or more logical blocks. Some of these may be "fully implemented" hard macros, but many of them may be pre-existing soft blocks whose behavior has been characterized but whose final physical and timing attributes have yet to be determined. IC Wizard shapes and packs these soft blocks together within the context of the chip-level plan, based on metrics that include performance, area, and shape constraints.

Next, the software decomposes chip-level timing constraints to create block-level timing budgets, and allocates them to individual blocks within the global timing paths and their associated interconnect. Global routing further refines the chip-level plan, creating meaningful estimates of chip-level performance and die size very early in the design process.

IC Wizard performs the steps mentioned above automatically or semi-automatically. Without this, it would not be feasible to work with fifty or more blocks. This allows a back-end team to prepare physical templates of constraints in advance, to which a front-end team may add appropriate parameters, for use during early front-end exploration.

Physical parameters from the chip-level plan may be used to constrain the logic synthesis of the RTL soft blocks. Since the designers know the shape, placement, and attributes of each port -- location, layer, loading, and resistance, the constraints they feed to logic synthesis are much more accurate than the purely statistical estimates that historically have been used to drive synthesis.

Once a design team synthesizes and optimizes all the RTL (soft) blocks, it can optimize the hierarchical structure of the design for physical layout. IC Wizard groups the fifty or so logical blocks into physical partitions, each containing anywhere from 50,000 - 500,000 gates. The software then automatically shapes these physical blocks, resolves overlaps, assigns ports, and adjusts timing constraints to reflect the new hierarchical structure.

If a designer needs to make a change, all he or she has to do is backtrack the genealogy of the hierarchical structure to the point where the change can be localized to a single logical block. After making the change, the designer can re-apply the hierarchical transformations used to optimize the design for physical layout.

The designer then exports the shape of the block and the port constraints to a gate-level place-and-route tool. The resultant blocks will possess "hard" physical and timing attributes. The designer imports the hard blocks back into the chip-level plan and IC Wizard adjusts the design plan to account for variances between the estimated block implementation and the real one.

The promise of design reuse -- faster turnaround time and improved productivity -- is often negated by the unpredictable nature of combining RTL blocks with other disparate pieces of logic onto a complex IC or SOC. However, designers who adopt block-based design planning and successive refinement techniques are indeed reaping these benefits.

Jacob Greidinger is executive vice president and CTO at Aristo in Cupertino, Calif. Greidinger has held R&D management positions at Compass Design Automation, Mentor Graphics, Silicon Compiler Systems, and Daisy Systems. He is a native of Israel.