Managing the IC Power Revolution

Electronic News, Feb 14, 2000 by Bill Chew

One of the fastest growing segments within the analog semiconductor arena is in the realm of power management. According to Dataquest, a member of the GartnerGroup, power management will have a compound annual growth rate of 16 percent over the next couple of years. With this in mind, and with many new opportunities emerging, it is certainly an exciting time to be a power management designer.

The market for power management has recently experienced company consolidations where interdisciplinary expertise has merged: new materials and circuit technologies that allow solutions at lower voltage nodes and higher currents and the integration of functions that now provide solutions with higher differentiation than ever seen before.

The growth in power management results in part from key end-equipment markets like telecommunications, PCs and Internet connectivity. Arguably, however, one of the most important factors in the power management boom is the explosion of end equipment, whose engine is powered by two different voltages. The portable consumer market is the largest example of this and includes devices such as cellular phones, audio players, personal digital assistants and digital cameras.

It is the proliferation of these unique, multivoltage "power-sensitive" devices that foretell continued prosperity within the power management market. However, these applications will also bring significant challenges for the designer and provider of power management ICs as battery-operated devices must cut energy requirements as much as possible in a market where feature-rich products give a competitive edge. For portable devices, power efficiency is as high a priority as it has ever been and the need to fuel higher performance over wider ranges of loads and lower voltages in smaller packages are all important in creating the most efficient system solution. These requirements pose daunting power management challenges.

At the heart of most of the portable equipment is a digital engine running off two different supply voltage rails -- typically a digital signal processor (DSP). Over the years, these digital engines have undergone numerous generations of die shrinks and performance improvements. The cores of many of today's DSPs, field-programmable gate arrays and other processors require very low voltages, and often run at sub-2 volts. At the same time, system peripherals such as memory and logic are being powered off an I/O voltage rail, which is typically 3.3V. The result: what is known as a split-rail (dual-supply voltage) solution is needed to handle both the lower core voltages and the 3.3V for the peripherals. However, that's not all you need to know about split-rail power supply design.

Sequencing in a Nutshell

One area to seriously consider in dual-supply voltage solutions is something known as sequencing. Sequencing is the relative voltage and timing of core and I/O voltages during power up and power down operations. There are two concerns that make this an essential part of every good power-management design practice: bus contention and current flow in the isolation structure between the core and I/O.

Bus contention between the core and I/O pins of the digital engine and the peripheral devices is most important. Sequencing should be considered and implemented to prevent bi-directional I/O pins of the core and a peripheral device from opposing each other. Since the bus control logic originates in the core section, powering the I/O prior to the core may result in simultaneous configuration of the core and peripheral pins as outputs. If the data values on each side are opposing, then the output drivers contend for control. Excessive current will flow in one of the paths, depending on the opposing data-out patterns. Powering the core at the same time or before powering the I/O prevents undefined logic-state on the bus control signals.

Bus contention may also occur during power down. If the core is powered down before the I/O, the bus control signals become indeterminate, which opens the possibility of excessive current flow through the DSP and peripheral output drivers. Proper sequencing includes both core-up first and core-down last with respect to the I/O supply.

The second reason to implement a sequencing strategy into your design is that the core and I/O blocks are isolated by structures that may become forward-biased if the supply voltages are not at specified levels. During power-up and power-down operations, differences in the starting point and ramp rates of the two supplies may cause current to flow in the isolation structures. Over time, this load on the structure will reduce the useable life and reliability of the device.

Without sequencing, tight restrictions must be placed on the voltage differential between the supplies to ensure reliability. To avoid this problem, systems should be designed so that neither supply is powered up for extended periods of time, if the other supply is below the proper operating voltage. Texas Instruments has an ongoing collaborative effort between its DSP and power management divisions whereby it is able to anticipate, avoid and solve situations such as those outlined here. These efforts not only result in the development of DSPs that do not require sequencing, but also in the development of power management ICs that solve such design issues in advance of market demand.