Supporting New Design Rules

Electronic News, March 5, 2001 by Bill Alexander

MONTEREY DESIGN SYSTEMS

SUNNYVALE, CALIF.--The continuous and relentless advances made by the semiconductor process and fabrication technologists have spurred enviable growth and a plethora of new devices. These new devices provide greater access to information, which, in turn, allows for tremendous improvements in productivity and personal quality of life. It's well known that as semiconductor technologies advance, manufacturable dimensions get smaller, enabling many more active components to be integrated onto a silicon chip. This allows complex systems to be made available at very low costs, which spurs the electronics industries, and, as a result, improves world economies.

However, this rapidly growing electronic market segment is facing very large technological challenges to maintain the productivity and yields that the market depends on. The biggest challenges in the design cycle are dealing with the physics and design rules in laying out chips for these advancing semiconductor technologies.

It used to be that manufacturing design rules were well understood and clearly documented so that the logic designers did not need to continually refer to them during the design of their chips. They would follow a set of rules that assured them a successful implementation of their designs and high manufacturing yields. The logic designers could focus their attentions on the increasing complexity of the chips they were designing and move even further into abstract representations of technology to manage the enormous complexities of these chips, which are systems. High-level abstract tools have been and are in development to enable the efficient design of systems-on-a-chip for very high-volume consumer and communication applications.

Although tools are available to help engineers create new designs for systems, a significant issue that must be considered is that for deep-sub-micron design; implementation of the designs has also become extremely complex. The tools have not been adaptable to manage the new requirements that are introduced at 0.18 micron and below. The physical layout and the implementation have become the bottleneck and inhibitor to continued technological advances.

An example of a new requirement m deep-submicron technologies is the antennae rule. Technologists introduced the rule to increase the yields of modern devices during the manufacturing process. As the dimensions have shrunk, the active devices, or transistor dimensions, have also shrunk to the point where the gate oxides are now very thin, only about 3.5 nanometers. Fabrication processes such as plasma deposition of materials can generate huge amounts of electrical charges to the extent that these thin gate oxides can be ruptured, destroying the active devices or transistors that are critical to the function of the circuit or design. The process of making the chip actually destroys the chip. Not a very helpful situation. As a result, the antennae rules were introduced. These rules define the dimensions of particular physical structures that are safe for successful manufacturing. The antennae rules also define how to correct a physical layout construct so that manufacturing will be successful, therefore produc ing a high-yielding chip at low cost and in the volumes demanded by the market. An example of this effect is shown in the diagram below (Fig. 1).

What a place-and-route system may do to connect inputs to a transistor is shown at the top of Fig. 1. This configuration violates the new deep-submicron technology rules as the length of the metal 2 wire that connects through metal 1 to the polysilicon gate exceeds the rules for this manufacturer. (The actual rules are somewhat more complicated, as they could be based on ratios of areas rather than lengths.) Basically, the length of metal 2 is such that it could accumulate enough charge to destroy the gate of the transistor it connects to because it is so thin. There is no way that any logic designer could possibly have known about this implementation for particular devices. This problem must be corrected in the physical implementation process. One way of solving this condition is shown in the lower part of Fig. 1. Here, the length of metal 2 is shortened by creating a contact to a short length of metal 3 and then bringing the connection back to metal 2. Now all the lengths of metal that connect to the sensi tive and thin polysilicon gate meet the charge accumulation or antennae rules for the manufacturer so that the part can be successfully fabricated.

More complex solutions are possible to avoid a situation shown in Fig. 1 and some of these involve the addition of active diodes connected to the metal connection that violates the antennae rules. This diode then forms the conductive path for the excess charge build-up and protects the critical gate of the transistor at risk. These sorts of additions warrant that the physical implementation process be called physical design. The place-and-route tools have to comprehend these rules and make adjustments for them so that the implementation is correct. If it does not, there maybe too many violations that cannot be fixed by a designer and the circuit will not be manufacturable.