Synopsys Taking Hold of Library Biz

Electronic News, March 20, 2000 by Gale Morrison

"History has shown that the large EDA companies have failed as channel partners due to a lack of expertise to support the libraries," said F. Taylor Scanlon, president and chief executive officer of Virtual Silicon Technology. He doesn't see a large EDA company like Synopsys getting its hands dirty with test chips at the foundry and constant interface with device engineers.

Synopsys hasn't made any physical library friends, and that was to be expected. "We are really trying to encourage (SIP and library vendors) to move up and differentiate their offerings," said Dworsky. Both he and Wolf at TSMC noted that Xemics Inc. of Geneva has done that already with libraries specifically intended for certain low-power and mixed signal applications. Being told to head for a niche area might not be what the likes of Artisan and VST wanted to hear though.

One thing can go unnoticed in this debate. Synopsys and all of the library vendors before it are acting at the behest of TSMC and Southeast Asia's other foundries. Wolf at TSMC said its library program had to come to pass because a focus was needed on the customer, the company who needs a semiconductor produced.

In the past, foundries were looking to get paid for getting a part to high-volume production, while for EDA firms and within the ASIC model the goal was to get paid for chip design software and engineering. TSMC devised a program called "Pay for Performance," wherein everyone gets paid once the customer reaches volume production. The library vendors, now including Synopsys, get paid only when the designs get back into customers' hands as silicon.

"Before there was a big gap between the library sale and the customer tape-out ... Now we all have a common goal and a focus on the customer," said Wolf. "We're in a good position to help the (chip design) industry be streamlined for our customers."

Maximizing its work in design and reuse and holding the commodity SIP space--by virtue of economies of scale and design and reuse investment, said Dworsky--fits into a larger Synopsys grand plan, too. System-level and high-level design will get more focus if designers aren't "engineering yet another PCI core," he said, echoing CEO and President of Synopsys Aart de Geus' words to Electronic News (see Jan. 3 issue).

Not That Way

Mentor is betting that the percentage of systems house design teams who go with programmable logic for new projects is going to keep rising. Its move out of a business getting increasingly commoditized and standardized (through Synopsys and Mentor's own great joint efforts to get everyone on the same Reuse Methodology Manual page using OpenMORE ratings) was the right one, said Mick O'Brien, general manager of the Inventra IP division of Mentor.

Quoting research numbers that field-programmable gate array (FPGA) design starts to outnumber ASIC design starts by three to one, Mentor has made FPGA design a major strategic focus and backed that up with the offerings of its HDL division. The firm has struck a deal, to be announced also this week at IP2000, with Actel Inc. of San Jose to provide its commodity SIP as FPGA netlists, and is looking to do the same with the other programmable logic vendors.