Analog Design lifts the veil: First two products use 'not just another rehashed EDA algorithm' - Design Strategies - Product Announcement

Electronic News, April 1, 2002 by Gale Morrison

Analog Design Automation Inc. (ADA) today is unveiling the first two products in its new Genius product line. Company executives said the line addresses the need to speed up and automate the custom and very high-performance SOC design segment.

The announcement is noteworthy for a couple of reasons, said Matthew Raggett, CEO of ADA. One, it offers a way up the productivity curve for the thorny and time-consuming transistor-level simulation and manual layout design flow that, increasingly, is being called into action as design teams tackle more and more mixed signal designs at very, very high frequencies. And two, it supplants EDA's conventional simulated annealing algorithm for crunching tool output with afresh-from-R&D intelligent systems approach.

Reading between the lines reveals a third, unstated reason of note: use at Intel. ADA has not discussed customers publicly, but Raggett did mention in February that he was talking with some guys at Intel the other day and, more importantly, Intel Capital is one of ADA's backers.

It's well known by now that Intel throws venture funds behind technologies for only two reasons: It wants or needs it internally, or it will expand the markets it sells into. ADA is clearly the former, as Intel is spending hundreds of millions of dollars right now to truly break into fast networking gear and wireless handsets in a big way.

ADA filed eight patents on this intelligent systems approach to analog optimization and synthesis, Raggett said. The unique algorithm came from work done at the University of Saskatchewan in Canada and can be applied to other tasks with hundreds of variables and hundreds of objectives, he said, such as optical network optimization and gene sequencing.

The key is it's not EDA's simulated annealing approach, which Raggett said is the key differentiator between what ADA is doing and what Neo-linear Inc. of Pittsburgh has been doing with much success, particularly in Japan and Europe.

"Neolinear is very similar to us," Raggett said, "the difference being their simulated annealing type of approach and the use of a traditional EDA algorithm. That tends to have certain limitations for multidimensional problem solving.

"We're dealing with maybe 100 to 200 variables and 15 or 20 objectives. Simulated annealing breaks down at that level. (It) could handle maybe 40 variables," Raggett said.

The tools push a customer's circuit simulators in parallel and come back to the designer with a library of solutions, he said. ADA's tool, called Creative Genius, then catalogs those solutions, and one can explore and analyze them with the second tool, IP Explorer Genius.

"The typical flow might produce one design that works. We'll produce, on average, 100 to 150 solutions that meet or beat the design spec," Raggett said.

Well-connected bank analyst John Barr said he likes what he sees in ADA.

"The Genius line of products is a solution that is coming at just the right time to address a definite need in a fast-growing market segment," Barr said. Barr is an EDA analyst with Robertson Stephens Inc. in New York.

"We believe that a new class of analog design tools could lead to strong growth for this traditionally underserved tool market. We believe analog and mixed signals synthesis tools could see growth of about 50 percent over the next few years, well above the EDA average growth rate of 15 percent."

Creative Genius builds its database of circuit IP from a transistor-level netlist, test benches, objectives, process and environmental variations and variables. The netlist comes from a schematic created in either Mentor Graphics' Aldo environment or Cadence Design Systems' Virtuoso-centric environment, and the designer supplies the test benches.

Every circuit that Creative Genius generates is passed through and verified by the designer's circuit simulator.

"It would take a designer several months to come up with all the circuits Creative Genius can produce in a matter of hours," said Amit Gupta, ADA cofounder and VP of business development. "Since our algorithms can handle all the values simultaneously, we can push the limits of the designer's objectives. Once the optimization run is set up, all the designer has to do is evaluate the solutions and pick the one that best fits their requirements."

Designers may evaluate the solutions and performance tradeoffs with the IP Explorer Genius tool, which displays an N-dimensional color graph showing all the results, where N is the number of objectives the designer has specified.

ADA is not releasing pricing on the tools.

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The Gigascale Silicon Research Center at UCBerkely.

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