Solving Post-layout SOC Verification Problems

Electronic News, April 23, 2001 by An-Chang Deng

As system-on-a-chip (SOC) designs exploit process technologies at l8Onm and below, these high-speed circuits increasingly exhibit nondigital behavior, including cross-coupling noise, inductance effects, electromigration and more. Consequently, detailed full-chip, post-layout verification with power and noise analysis becomes imperative for achieving working silicon for these nanometer designs. Yet, as SOC designers attempt post-layout verification and analysis of complex nanometer circuits at the final stage of a design-verification cycle, they face a huge amount of extracted parasitic data. Besides significantly slowing down the post-layout verification process, multiple gigabytes of resistor, capacitor and coupling capacitor data extracted from a layout also typically exceed the analysis computer's memory capacity--making post-layout verification of SOCs impractical in existing design flows. In contrast, hierarchical approaches can enable the post-layout, full-chip circuit verification and analysis needed t o ensure working silicon in complex SOCs.

Designers face an explosion in the volume of parasitic data due to the flat-extraction approach employed by most available layout extractors on the market. The flat netlists produced by the traditional extraction approach simply become impractically large when circuit size increases to SOC complexity. For example, a full-chip flat extraction of a 2Mbit SRAM results in a file size of 5Gbytes containing 13 million transistors and 50 million parasitic resistors and capacitors (RCs) --and the number of parasitic RCs and the associated netlist file size increase at least linearly with circuit size.

Unfortunately, the capability limit of existing analysis tools is typically on the order of 1Gbyte, requiring designers to search for alternate strategies for post-layout verification. Traditionally, designers have attempted to deal with this problem through flat extraction of a subcircuit block so that the extracted file size remains within the capacity of their analysis tools. Although they can separately verify each subcircuit block in this manner, SOC designers, of course, have no guarantee of working silicon due to the complex interactions that extend beyond the subcircuit blocks they are able to verify using this method. Designers have also tried to manually estimate the interconnect resistances and capacitances in the prelayout netlist, but this type of crude estimation significantly compromises the accuracy of the results.

Other alternate approaches use delay calculation on the extracted RCs with annotation of the delay values to gate-level simulators or static-timing analyzers. Although this method addresses the requirements for timing analysis, it models resistances and capacitances as timing delays and consequently lacks the electrical data needed to perform power analysis or noise analysis. Similar problems apply to mixed-level methods where SOC designers work with individual design sections represented by models at different levels of abstraction.

Although the existing ASIC approaches work well for functional verification and possibly timing analysis, their inability to deal with today's huge amounts of extracted RC data and to provide power and signal-integrity analysis makes them unsuitable for nanometer designs. Instead, hierarchical approaches remain the most feasible solution for achieving manageable post-layout data volume for circuit verification and detailed analysis before tape-out.

One approach involves back-annotation of extracted flat-parasitic data to a hierarchical prelayout circuit netlist followed by hierarchical verification with layout parasitics in a similar fashion. With the net-by-net format in the detailed standard-parasitic format (DSPF), back-annotation of parasitic RCs into the device netlist can be very flexible. For example, designer can selectively annotate critical nets only, or skip resistances and annotate capacitances only for those nets with negligible resistances when compared with driver impedances.

A better approach is to extract hierarchical parasitic data followed by simulation and analysis using a hierarchical full-chip circuit simulator. In this approach, the extractor can follow the layout hierarchy to produce a hierarchical netlist, which has a significantly smaller netlist file size than the flat netlist file size. The circuit analysis tool then performs the hierarchical circuit analysis on the extracted netlist. Unfortunately, although designers do create hierarchical netlists manually for some high-volume products such as memory, existing commercial layout extraction tools do not support hierarchical extraction.

For nanometer SOCs, designers hay no assurance of desired silicon success without post-lay-out, full chip, circuit-level verification along with associated power and noise analysis. Because of the large amount of data and analysis time, flat approaches fall short of designers' needs in today's SOC era. While hierarchical extraction is efficient, it will provide no real advantage in analysis time unless the analysis tool performs hierarchical circuit analysis. Hierarchical extraction and analysis are supported by a limited number of tools today, but hierarchical approaches are the trend--and the only alternative for achieving silicon success for nanometer SOC designs.