Higher-Level Languages, or More Hardware for SLD?

Electronic News, April 30, 2001 by Jason Andrews

Design verification has quickly evolved into one of the most critical steps in the system-design process. Recent studies now indicate that as much as 70 percent of the design cycle is now spent on verification. Two stories have grabbed most of the attention this year: system-level design (SLD) and hardware-based verification.

It's All About Change

The SLD story has shifted the focus from bits and bytes to packets and protocols. A number of new SLD languages have been proposed to raise the level of abstraction and to unify the system architects, hardware engineers, software developers and verification engineers through the use of a common language.

The goal of this higher level of abstraction is to explore the design space and make choices regarding the implementation quickly so that the detailed work can begin on the feasible alternatives. These choices can include the processor architecture and performance level, memory subsystem characteristics, peripheral set, special hardware-acceleration functionality and bus structures.

For software, design issues such as real-time operating system scheduling and architecture must be decided. The generalized SLD flow is to capture design requirements, work out algorithms and data flow at the behavioral level, partition the behavior into hardware and software, make choices about the target platform, estimate how well the proposed solution meets the requirements, and iterate until the solution meets the requirements. Once the requirements are met, the software development and register transfer level (RTL) design can begin.

Many tools have been introduced to make the benefits of system design a reality. Early adopters of this methodology have already realized many of its benefits. But what are the critical issues engineers should be looking at when evaluating where to start with this new methodology? Are there incremental steps that can be done to optimize the design flow while minimizing risk?

The major issue for many hardware designers is language. While Verilog and VHDL knowledge will always be needed, engineers that can understand C and other system design languages such as specification and description language and UML unified modeling language will be needed. For system-level design to be successful, many engineers will need to add these skills. Companies that provide C class libraries and macros to make C look as much like a HDL as possible clearly attest to this. In addition to a shift in languages, working at the system level introduces a new set of concepts, buzzwords and acronyms--interface synthesis, communication channels, models of computation, semantic domain and hardware/software partitioning, to name just a few.

The next major hurdle for SLD is building the complete design environment with all of the integration and interoperability. Compare the current level of SLD interoperability to the Verilog PLI, a standard in RTL simulation environment. A quick look at the verification environment used on any ASIC project makes it clear that a lot more than a language and a simulator is needed. Engineers have assembled a multitude of third-party tools, models and scripts to bind together everything necessary to get the job done.

Once a robust environment for simulation is achieved, the synthesis path to hardware will be the last remaining hurdle for true top-down, system-level design. Transforming this process from a translator-based solution into a true behavioral synthesis will complete the SLD flow.

Even with this current set of challenges, SLD offers great promise in transforming the RTL design process of the 1990s into a coherent flow that begins at the behavioral and specification level and which is continuously validated down to the implementation level.

Performance is King

A more immediate solution to address today's verification challenges is the use of hardware to break through the bottlenecks of design verification. A hardware solution offers incremental benefits with only minor changes to existing design flows and has become a very practical stopgap for many projects.

In hardware-based verification the phrase "performance is king" has never been more accurate. With software simulation running out of steam, new solutions for simulation acceleration, hardware modeling and ASIC prototyping have been deployed on an increasing number of projects.

While simulation accelerators have been in existence for many years, new methods that offer improved performance and debugging at the RTL level with full visibility of the design are attractive for those engineers that are comfortable working in Verilog and just want more speed. Running 1,000 times faster without changing languages or losing any simulation detail is extremely valuable.

After a decade of HDL simulation and expensive hardware emulators, engineers are returning to prototyping as a key part of ASIC and system verification. This change was fueled by developments in the FPGA arena. Both Xilinx Inc. and Altera Corp. are now offering devices with more than 1 million gates. New RTL partitioning tools work on a design at the RTL source-level and can optimize the design across a set of FPGAs for performance, area and I/O interconnect. Add it all up and the answer is a way to build a custom emulator for a fraction of the cost of commercial prototyping and emulation systems. These prototypes can provide great benefit for software testing, early system demonstration and test marketing. Software engineers love to run on real hardware and can't stand slow simulation speeds. The ultimate design verification has always been to run the system software.