ARM's Next Thumb

Electronic News, Oct 26, 1998

San Jose-Advanced RISC Machines (ARM) has rolled out its next- generation Thumb microprocessor intellectual property (IP) core, dubbed the ARM10. It features a claimed performance level of more than 400 MIPS.

The core is targeted at consumer applications such as digital set-top boxes and next-generation high-performance hand-held devices including organizers and smartphones.

Of the more than 200 IP providers in the market today, ARM was one of the earliest and has made a business out of selling MPU cores to various semiconductor vendors. The company has seen its Thumb cores integrated into various applications-specific ICs (ASICs) from a variety of logic vendors, in multiple consumer electronics products on the market today.

ARM is also one of the few companies making a profit in the IP market due to the wide acceptance of its cores in the electronics market. With the introduction of the new ARM processor, the company hopes to continue its MPU core leadership, despite the mounting competition it faces from some of these other 200 vendors.

Part of the reason for the success of the ARM may be because the company claims the Thumb cores enable reduced system complexity, increased flexibility and a low-cost, high performance macrocell that can be ported across multiple fabrication processes. The new ARM10 core is said to deliver 400 MIPS at 300MHz and features an optional vector floating-point unit capable of delivering 600 MFLOPS. This floating- point unit allows for interfaces with 2-D and 3-D graphics rending for video game players and high-performance printers. The ARM10T is scalable to 0.25, 0.18-micron-and-below geometries.

In a bid to get its new IP into this fast-churning market quickly, ARM is slating initial prototypes of the ARM10T core for release by mid- 1999. The ARM1020T will be the initial core in a planned family of ARM10 Thumb cores which will be compatible with the ARM7 Thumb family of cores as well as the StrongARM processors, thereby providing software and process compatibility across a spectrum of performances ranging from 60 to 400MIPS.

The ARM1020T features two 32KB caches, twin 64-entry translation look- aside buffers and includes memory management functions for full demand- paged virtual memory operating systems and real-time embedded system operations.