Mentor And Cadence Integrate Design-For-Test, Synthesis Tools

Electronic News, Oct 26, 1998 by Ann Steffora

A standard feature to insert test circuitry and start automatic test pattern generation in conjunction with initial synthesis

Washington, D.C.-The proliferation of intellectual property and the complexity surrounding today's complex designs is requiring users to create Design For Test (DFT) methodologies. In support of this idea, Mentor Graphic's DFT Division and Cadence Design Systems announced last week at the International Test Conference an agreement to integrate their industry-leading DFT and synthesis products. Cadence obtained the BuildGates synthesis tool from its recent acquisition of Ambit Design Systems.

This announcement is an extension of an agreement made at this year's Design Automation Conference, where Mentor and Ambit agreed to link tools.

As a result, design engineers will be able to insert test circuitry and start automatic test pattern generation (ATPG) in conjunction with initial synthesis. This is possible through the integration of Mentor Graphics FastScan ATPG technology with one-pass scan insertion technology from the BuildGates synthesis software. This capability has been available in BuildGates since early this year. Other logic synthesis tools do not contain this feature as standard, but rather as an add-on.

Files required to run the FastScan tool for test generation during test synthesis can be automatically output enabling ATPG tests to be part of the single-pass test synthesis flow. This automation eliminates the hand-editing process using traditional methods, required to move from synthesis to manual test.

With the full-scan insertion feature in BuildGates, this puts test into the heart of the logic synthesis process, leading to a single-pass approach, increasing productivity and performance.

"Open technology partnerships are a strength that Cadence's Connections program brings to our customers. Test is one area where we have chosen to partner with technology leaders in order to complement our product offering. By working with Mentor to integrate their ATPG technology into BuildGates, our mutual customers can expect a tight solution to ensure high-quality, testable designs," offered David Milam, VP of product marketing, Cadence.

New Technology, Tools

In addition to its expanded partnership with the BuildGates tool, Mentor Graphics announced new built-in self-test (BIST) software for testing high-performance, multi-frequency electronic systems at true operating speeds. Mentor Graphics also announced new technology to insert BIST into complex memories in one easy step, aiming to shave weeks off test development times. The combination of this technology and the application innovation in the area of self-test for electronic systems allows engineers to reduce the cost of manufacturing test while increasing the reliability and quality of new products.

Mentor Graphics' patent-pending, at-speed, multi-frequency BIST technology is being incorporated into its logic BIST synthesis product, LBISTArchitect. The tool is targeted at engineers designing integrated circuits (ICs) that contain more than 20 clock domains running at 66MHz and 155MHz, typically found in high-performance telecommunications, digital entertainment and data-processing systems.

These memory BIST advancements allow designers to insert BIST circuitry into complex memories in one step, cutting test development times.

Customers are already responding. "BIST is an important part of our future to ensure quality for both ASIC and system-on-a-chip designs. True at-speed testing is a critical issue because it dramatically impacts product reliability. Mentor Graphics' new BIST technology is an attractive solution that addresses our primary test concerns: product cost and reliability," noted Greg Young, member of group technical staff at Raytheon Systems Co.