Aristo Attacks Block-based Design

Electronic News, May 17, 1999 by Ann Steffora

Cupertino, Calif.-Start-up Aristo Technology Inc. this week is introducing its IC Wizard Floorplan Synthesis tool, which can automatically create and optimize design alternatives at the floorplanning level of a design cycle.

IC Wizard's floorplanning design methodology addresses the increasing complexity and size of ICs. The floorplanning approach, also known as the block-based, or the core-based design methodology, enables extremely complex ICs to be created by using a level of abstraction that is at a high enough level to allow for management of the blocks. IC Wizard provides estimates of what the physical information will be when the design is completed.

This differentiates IC Wizard from the majority of today's design tools, which are not capable of floorplanning.

The biggest benefit to the tool may be the learning early on if a design will be viable, so that the design can be stopped or altered to fit the intended application. For this purpose, IC Wizard provides data to assist with system and architectural partitioning, performance assumptions, block budgeting, implementation and process and silicon IP core selection.

According to Aristo, the tool generates physically valid, timing correct floorplans that can help with router congestion, in comparison to traditional semi-manual block planning methods.

Another benefit to the tool is that it fits in with existing Cadence Design Systems and Synopsys design flows to bring added optimization. IC Wizard reads in Verilog, VHDL and GDS2 file formats.

Already, graphics processor companies ATI/Chromatic Research, GigaPixel Corp., and design services provider AppNet are using the tool with some success, and all expect that the tool will help accelerate time-to-market.

Currently in beta, the tool is slated for general release in July on Unix and NT platforms, with prices starting at $100,000.