Fujitsu Embraces Tera Design Planner : Semi vendor will implement as part of IPSymphony design environment

Electronic News, May 24, 1999 by Ann Steffora

Scottsdale, Ariz.-With timing convergence being one of the key challenges to system-on-a-chip design, start-up Tera Systems Inc., Campbell, Calif., has landed Fujitsu Limited and LSI Logic as customers for its tools.

Fujitsu will be incorporating the company's technology into its SOC design environment called IPSymphony. In addition, LSI Logic has started using Tera's TeraForm tool in its design environment.

With SOC designs, it is important to learn early in the design process what physical effects will occur, including the impact of wiring delay on timing. By addressing these issues at a higher level, designers can analyze and control important parts of the design in order to reduce subsequent iterations, said Richard Gordon, executive vice president and co-founder of Tera.

What is important to remember when looking at different approaches is how quickly you can reach timing convergence, and if the design is scalable, said Gordon.

"TeraForm uses a 'prescriptive' versus 'predictive' approach as many competing tools do and architects performance into the register transfer level of design, instead of tuning at the gate level."

Given the many options hitting the market today, another issue to consider is 'What solution are you looking for?' suggested Tommy Eng, president and founder of Tera Systems.

"If you believe the world consists of blocks, and want to let a tool do the floorplan and detailed route at this level, there are tools on the market to do that," he said. "We do not believe this world has arrived. It is difficult to reach timing convergence without looking into the blocks," Eng continued.

Looking into the blocks gives the ability to learn about the interconnect between blocks and therefore partition a design, enabling interactive design, which scaling to SOCs requires, he said. Scalability goes beyond just cutting time, it also includes integrating synthesis with physical design, and the ability to design and debug in real time.

TeraForm accelerates the ever-so-critical timing convergence for high- speed SOCs by budgeting full-chip timing and by using placement-based parasitic data instead of statistical, or predictive wire load models during synthesis, Gordon said. The tool does not try to predict synthesis, rather, it figures out what is achievable and creates a blueprint for building the design, he added.

Fujitsu is in the process of qualifying TeraForm for its CS71 0.25- micron library, and expects to make the tool available to its IPSymphony process later this year.