Synopsys Enters Physical Design Market

Electronic News, Feb 1, 1999 by Ann Steffora

With its new Chip Architect, #2 EDA vendor ties together synthesis and placement

Mountain View, Calif. -- Synopsys unveiled its long-awaited Chip Architect Design Planner tool last week, along with its strategic plan for integrating logical and physical design, which it is calling "physical synthesis."

The new product will compete with offerings from Avant! and Cadence. Chip Architect Design Planner could potentially provide Synopsys'sDesign Compiler users with a new top-down design flow for accounting for physical effects of a design, the intended result being less iterations and faster time to market.

Toshiba Corp., STMicroelectronics, and Matsushita Electric Industrial Co. were present at the rollout to describe the results from their implementation of the tool.

"These are some excellent preliminary results from the customer data," noted Erach Desai, a financial analyst with CS First Boston, also was also encouraged by Synopsys' development of the tool capabilities internally. "It was thought that Synopsys had some disjointed technology it was licensing from IBM, but they stepped away from that and developed it on their own."

Desai also believes that since the company holds a leadership position in the front-end of the design process with Design Compiler, this puts them in the best position to understand the customer base they are addressing with Chip Architect.

For OEMs designing systems-on-a-chip, architectural issues relating to process technology and complexity changes are presenting new challenges to design engineers. One of those challenges is to have an early understanding of timing, in order to better assess predictability and performance of a design, said Aart de Geus, Chairman and CEO of Synopsys.

Since chip designs at 0.25-micron can be as large as 10 million gates, a top-down design style is the way to proceed through the flow, from pre-synthesis planning to physical implementation, giving more predictable indicators, heexplained.

Traditional design handoff from logic synthesis to place-and-route is becoming unmanageable, and causes multiple iterations before tapeout. Top-down design planning attempts instead to proceed from pre-RTL design conceptualization to logic and through placement, ensuring that the placed logic gates are routable.

Timing Is the Backbone

Synopsys' Physical Synthesis strategy uses timing closure as its foundation, integrating the Chip Architect Design Planner, the Design Compiler logic synthesis tool, the Module Compiler tool and a new top- level routing technology. The capabilities of the top-level routing technology, which Synopsys gained with its acquisition of Everest Design Automation last October, will be introduced at some point this year, Synopsys estimated.

The Chip Architect users agreed that incorporating the technology into existing design flows was relatively straightforward since the tool uses open file formats

The tool includes features such as a hierarchical floorplanning, embedded static timing analysis, breakthrough timing-driven detailed placement and global routing.

Other features of the tool include RTL estimation, clock-tree synthesis, power network planning, congestion analysis, gate-level optimization, support of standard interfaces and proven flows with existing place and route tools. Synopsys said the tool is reported to run best with IC designs larger than 500,000 gates and running at more than 100MHz implemented on advanced silicon processes of 0.25-micron and below, and especially for users of Synopsys' Design Compiler and PrimeTime products.

Synopsys currently is working with approximately 11 semiconductor vendors to implement the Chip Architect tool within existing design flows, a list de Geus expects will grow to 26 companies very shortly. The tool pricing ranges from $100,000 to $250,000, depending on features and services provided.

"This has been a long time coming," noted Jennifer Smith, a financial analyst with BancBoston Robertson Stephens, who said this announcement is positive because of the strong customer endorsements which Synopsys has been working on for a period of time. "The EDA industry has been focused lately on merger and acquisitions, hostile takeover and the like, that (the industry) lost sight of collaborative partnerships."