Timing Closure: It's All About Electrically Correct Designs

Electronic News, Feb 1, 1999 by Shashank Goel

Santa Clara, Calif.

Managing timing -- its predictability and closure -- is now the mission critical success factor for engineering managers in system houses and fabless semiconductor companies. Timing closure refers to the matching of clock and signal performance in actual silicon and systems with the original estimated timing requirements specified by the IC and system architects.

As very deep submicron (VDSM) semiconductor process technology (250 nm and 180 nm feature sizes) become prevalent, companies will employ system-on-chip (SOC) methodology to cope with complexity and time-to- market pressures, but design teams will face the timing closure gauntlet. The emergence of reusable intellectual property (IP) and the growing difficulty it presents for design verification poses significant technical and business hurdles.

Verification engineers outnumber design engineers by 3 to 1 on today's engineering teams and this ratio is simply not sustainable in the future. So, how does engineering management maximize productivity and profitability on key design projects in the face of these accelerating trends?

The real promise of VDSM technology is to enable the system-on-chip. However, today's SOC designers find themselves stonewalled by lost productivity brought about by archaic design tools and methods. They perform numerous iterations between logic synthesis and physical layout tools to reach timing closure which often squanders the real profits available from SOC opportunities. Those moving to SOC methodology encounter tremendous risks not only from missed market windows, but also from the over-conservative design practice of guardbanding and increased NRE costs of multiple silicon spins.

Greater productivity promised by SOC design methodology is only a partial answer to closing the gap between VDSM process capability and today's design tool capability. The remaining productivity chasm has to be crossed by true innovation in design tools and technology that supports accurate timing prediction and rapid timing closure between logical and physical representations. Backend physical verification approaches to resolving the timing problem through parasitic extraction and static timing analysis, while comforting as a final check before tapeout, are too cumbersome and late in the design flow to be effective.

Topology-based RTL floorplanning and chip assembly tools are a good starting point for organizing large designs, but are insufficient to achieve timing closure. Chip assembly tools need to intelligently minimize blocks to help manage block-to-block interaction. Unfortunately, the necessary physical design information is missing. Placement-based synthesis and common physical data models suffer from deficiencies as well. They consider timing fixed to one physical design image. This approach misses the fact that VDSM design is active element network design. Active element design assumes that wiring is limited, power is precious, and robustness and reliability are essential.

The variability in VDSM design is in the interconnect delay and capacitive coupling of wiring which must be modeled by active prototype routing rather than by the static wireload modeling typically used in today's floorplanning and automatic block/cell place & route tools. Augmenting topological approaches with timing constraints is not enough, because minimizing or eliminating timing iterations can only occur when timing analysis, physical placement, and circuit optimization work together as the physical design is formulated. Only then can timing, signal integrity, power and reliability all meet design requirements.

Today's SOC designers need to know whether the blocks in the floorplan can be formulated with the correct electrical placements on the chip. They need to have an electrical abstraction of the design before getting to the detailed layout stage.

Any notion of a design solution that delivers timing closure must incorporate all the electrical effects that introduce timing variability.

Shashank Goel is President and CEO of Sapphire Design Automation