Time Is On Our Side

Electronic News, Feb 8, 1999 by Michael (American pop singer) Jackson

Fremont, Calif.

Would you ask directions of a stranger from out of town? Probably not, especially if you were interested in reaching your destination. This is the kind of question that design teams should be asking themselves about recent Chip Architect product announcements made by logic synthesis company, Synopsys, regarding its foray into the mission- critical implementation side of chip design.

Fundamentally, the objective of Chip Architect is sound - drive predictability into the synthesis process. In fact, Avant!, as a long time consumer of synthesis results and ardent supporter of Synopsys' Design Compiler, has been driven by customer requirements to develop technology that manipulates synthesis output so it will faithfully represent the design when implemented in Very Deep SubMicron (VDSM) silicon. For example, Avant!'s Saturn Physical & Timing Optimizer has had logic synthesis optimization technology in it for over a year and our Planet-RTL floorplanner, now in its second generation, included built-in fast-synthesis back in 1998. Speaking from the perspective of more than 5,000 production-proven VDSM chips, Synopsys claims that first-generation placement algorithms included in a logic synthesis product qualify it to provide an authoritative view on chip implementation invite skepticism.

Does global routing and placement integrated with logic synthesis go far enough? In our experience, doing only part of the job in VDSM design creates a dangerous false sense of accomplishment that can lead to costly mistakes late in the implementation process and hardly seems a reliable strategy for shortening the design process and improving quality of results.

Let's assume for a moment that a design floorplan done with Chip Architect is passed on to Avant!'s Apollo place and route software. The first thing that the engineer who receives the Chip Architect floorplan is going to do is a placement and global routing - using the Apollo algorithms. The chance that a Chip Architect placement and global routing correlates with Apollo and addresses real VDSM physical issues is extremely remote. And since it's Apollo that will be used to do the final placement and routing, those are the algorithms on which the designer will "bet the chip". So, if the algorithms used in floorplanning are not correlated with those of the place and route software, it's not clear whether the results of floorplanning have any relevant value or even whether they represent an optimal physical implementation from the standpoint of timing and area.

Yet, the objective of driving predictability through the synthesis process indeed promises significant reductions in design cycle time and quality of results. That's why Avant! has incorporated its patented layout algorithms and expertise - the very same algorithms used by Apollo - into its pre-synthesis Planet-RTL floorplanner. But experience shows that common algorithms alone are not enough to guarantee predictability from synthesis through physical implementation. Planet- RTL also shares a common database - Milkyway - with Planet-PL for post synthesis physical floorplanning, Apollo for place and route, Mars-Rail for electromigration analysis, Mars-Xtalk for noise and interference analysis, Saturn physical optimization, Star-RC parasitic extraction, Hercules physical verification, and Taurus-OPC - elements critical to the RTL Virtual Prototype as defined by Dataquest's chief industry analyst, Gary Smith. As a result, floorplan results are correlated with place and route by definition and the data structures supporting the floorplan view are the same that will be used throughout implementation even to the final GDS II files and optically correct mask sets.

Avant! recognizes that successful efforts to drive predictability in a VDSM design process begin long before synthesis or RTL floorplanning. Significant productivity improvements and more predictable designs begin with structured Design Authoring. Avant! offers a comprehensive line of pre-synthesis RTL simulators, syntax and style checkers - including the only design automation software that creates a structured design flow around the guidelines of the Synopsys and Mentor Graphics Reuse Methodology Manual - and is preparing to introduce a family of solutions that take a fundamentally new, VDSM approach to the complex issues of pre-synthesis, structured Design Authoring.

Michael Jackson is Head of Product Management for Avant! Corp.