ARM Supports CoreFrame Architecture For SOC Designs

Electronic News, Feb 8, 1999

Los Gatos, Calif.-ARM said last week that it is supporting PALMCHIP's CoreFrame Architecture for system-on-chip (SOC) design. The architecture was developed to provide a high performance on-chip interconnect methodology that allows silicon functional blocks to be combined together quickly and easily. The technology expands the range of implementation options available to system-on-chip developers and complements ARM's own AMBA system-on-chip bus standard.

ARM said the CoreFrame Architecture provides a proven system-on-chip connection methodology for data intensive designs, and adds to the range of system-on-chip technology supporting the ARM architecture.

CoreFrame uses a shared memory architecture which is optimized for devices with high bandwidth data streams requiring extensive direct memory access (DMA). CoreFrame is synthesis-friendly and implements simple protocols to reduce system-on-chip design and verification time. By eliminating tri-state signals, CoreFrame can also reduce power consumption and allow higher clock speeds and data transfer rates. CoreFrame is interoperable with the established AMBA bus standard, allowing designers to mix and match virtual components to create customer-specific system-on-chip designs. For example, designers can build systems that combine an ARM CPU core and AMBA Advanced Peripheral Bus (APB) peripherals, together with CoreFrame DMA peripherals and high-speed memory interface.

With this capability, designers can designers select from a portfolio of intellectual property and combine them in the most efficient way. The CoreFrame architecture has been proven in silicon with a high performance hard disk controller, a CDMA and TDMA mobile phone controller, an Ethernet print server, and a general-purpose ARM-based microcontroller. PALMCHIP has developed ARM-based SoC reference designs for hard disk drive, DVD, mobile phone, networking and digital camera applications.