Selecting the Right Hierarchical Physical Verification Tool

Electronic News, Feb 15, 1999 by Greg Landry

San Jose, Calif.

Deep-submicron process technology offers tremendous opportunities for IC designers by extending transistor budgets and enabling new levels of performance to be reached. However, physically verifying multimillion- transistor designs presents unique challenges.

As the last quality-control step before an IC design is manufactured, physical verification must provide accurate analysis because additional manufacturing iterations impose unacceptable cost and time penalties. Traditional approaches are too time-consuming to accommodate shrinking time-to-market windows.

The Cypress design team confronted this problem when it began development of a new family of 4-Mbit SRAMs. Designing a 26-million- transistor memory, with a four-month time-to-market window, necessitated a new approach to physical verification.

The two typical verification techniques available - full-flat and partitioned - would force them to trade runtime for reliability. Traditional flat verification promises reliable results, though the team calculated this approach would produce unacceptably long verification times (e.g., 244 hours for design-rule checking). Clearly, there was no way a flat tool could tackle full-chip verification. Instead, the SRAM core and periphery would be handled separately, and designers would have to manually check the interface.

An alternative approach, hierarchical physical verification, promised significant runtime savings. Hierarchical verification takes advantage of repetitive layout and design patterns to speed through DRC and LVS. The team extensively researched whether hierarchical physical verification tools could deliver significant savings in full-chip verification runtime without sacrificing reliability.

Not all designs lend themselves to a hierarchical approach. For flat layout methodologies, as in ASICs, a flat verification approach makes sense, and a hierarchical tool needs to accommodate those cases. In addition, the verifier's LVS capability must deal effectively with the fact that the layout and schematic rarely match at every level. To effectively handle complex deep-submicron designs, the verifier should accommodate these variations, comparing layout and schematic accurately and without false errors.

In flat verification, errors in the interconnect between blocks are traced down to the device level, creating extremely long and frequently misleading error reports. A good hierarchical verifier should isolate block interconnect errors to the upper level, simplifying debugging and eliminating misleading error reports.

Physical verification does not happen in a vacuum. A well-crafted verification tool must fit into a designer's existing EDA environment, including schematic capture and circuit layout tools. In this way, designers can move easily from physical verification to debugging, layout and design, and then back again to verification. To allow this, the verification tool must build on a design team's investment in existing tools and rule sets.

After reviewing requirements and comparing competing offerings, the Cypress design team opted for Vampire verification from Cadence Design Systems, Inc. Since the team had used Cadence's Dracula and Diva tools, Vampire met the team's requirement for compatibility with existing tools. The availability of a Dracula-to-Vampire translator, as well as a rules translator from Diva, further smoothed the transition.

Validation of the decision and confirmation of the accuracy of the hierarchical approach didn't really come until the team achieved first- pass working silicon. By moving to a hierarchical tool, the Cypress team estimated that it cut full-chip verification run-time by 100 times, reduced verification cycle time by over 50 percent and slashed the overall design cycle by two weeks.

In an industry where time-to-market dictates success, such results indicate that hierarchical physical verification will soon become the preferred approach for large, complex designs.

Greg Landry is principal design engineer for Cypress Semiconductor.