EDA grapples with more languages: standards process still used for competitive purposes - Design Strategies

Electronic News, May 27, 2002 by Gale Morrison

While much of life is uncertain, one thing is for sure: There will always be EDA language wars, fought inside the standards bodies and inside engineering teams and between EDA software companies.

One week from today, the board of Accellera will vote on System Verilog 3.0, after a yearlong, highly intensive vetting by the System Verilog committee of the merged hardware design language (HDL) standards group. The effort is one of the most advanced yet in coming up with a language for system-level exploration, as well as design and verification.

EDA companies large and small are angling to use this process, and paying a lot of lip service to open-source code and standards, for their own competitive advantage. Powerful interests in EDA are backing different language or standards as it suits their needs, or one set of their customers' needs.

That means systems architects at the world's largest electronics companies must understand about 12 design and verification languages. The surfeit of languages has arisen for a number of reasons. For one, each language has its unique purpose and function in some respects, and many are either subsets or supersets of the others.

But other factors have played in. The commercial intellectual property market has matured, which means more and more companies are packaging and selling blocks of one code or another and moving them to the masses. Also, projects increasingly are geographically dispersed, so teams using different languages are mingling. In addition, the semiconductor industry has untethered a lot of its R&D and many, many projects start entrepreneurially -- often with the less expensive and/or more experimental approaches -- then must be completed after acquisition by a large corporation with a literal manual as to how design gets done.

At the Design Automation Conference (DAC) in two weeks, Cadence Design Systems Inc. will be talking a lot about its support for SystemC and the Accellera Sugar standard in products coming out this fall. Cadence 10 days ago sent an "open letter" to the industry calling for support of the OpenAccess design database based on its Genesis format. Yet, Cadence incurred Accellera's wrath when it very recently sought to put off the System Verilog vote saying, in essence, it needed more work.

It's clearly a remarkable time of transition for EDA design and verification languages. The industry has been struggling to get to a higher abstraction level for many years -- perhaps since designers moved up to the HDL abstraction level about 10 years ago. As designs have become monstrously large and complex, by virtue of how many transistors manufacturing R&D can now pack on a chip and the number of functions that engineers want them to accomplish, designers have brought up all manner of tools and language approaches to see that they are sure to work.

This has meant a field of pure hardware verification languages such as Synopsys' OpenVera and Verisity's e and the new Accellera standard Sugar, with Synopsys and Intel going their own way with their ForSpec language.

And the messy evolution of language approaches has meant several fits and starts to either expand upon or supplant Verilog and VHDL. In the mid-1990s, Verilog was the predominant language choice in North America, and VHDL was predominant overseas. Globalization has changed that dramatically, and more activity has been poured into Verilog successors.

Phil Moorby, chief scientist at Co-Design, recently told a high-level crowd in Japan that VHDL users are hitting a brick wall in engineering their designs and probably have to choose another path to follow. "Those VHDL users who are hitting the VHDL 'brick wall', can either join the Verilog/V2K/SystemVerilog/Superlog path bandwagon, or adopt an HDL-like C++ class library, of which SystemC appears to be an obvious choice," said Moorby.

And judging by Cadence's increasingly strong endorsement of SystemC, including its announcement today that several Cadence products are coming based around it, the European base is in fact coalescing around SystemC.

But that doesn't mean the overall EDA industry is following suit. Many members of the E-mail Synopsys Users Group (ESNUG) have posted their strong dislike for SystemC, and C/C++ design in general. The System Verilog vote next week will mean the endorsement of a great part of Co-Design's Superlog.