Transistor-Level Simulator to Ease SOC Verification Pain

Electronic News, June 7, 1999

Cadence Design Systems Inc., San Jose, last week introduced its Affirma accelerated transistor-level simulator (ATS), the company's first entry into the digital fast-metal-oxide-semiconductor market. Cadence said the tool is key to enabling verification of systems-on-a-chip (SOCs) and other large, digital-centric, mixed-signal designs.

This is the first product from Cadence's acquisition of the Lucent Bell Labs Design Automation Group aimed at providing a proven architecture for timing and power analysis of transistor-level mixed-signal designs. When linked with the Cadence Affirma interleaved native-compiled architecture's simulator, Cadence said the tool's capabilities are extended to mixed-signal, mixed-level (transistor to behavioral) verification for complex designs. Affirma ATS targets the improvements in design productivity and predictability required to verify advanced designs using state-of-the-art manufacturing technologies to 0.18- micron and below.