Discontinuities In Analog, Mixed Signal Design

Electronic News, June 4, 2001 by Walden C. Rhines

The following executive viewpoint authored by Walden C. Rhines, Mentor Graphics Corp. chairman and chief executive officer, for Electronic News addresses the first in a series of discontinuities that represent both the greatest challenges and the greatest opportunities in the industry--this one in the analog/mixed signal space. This is the first offour installments that will also include discussions of change in system-on-a-chip, board design and physical verification methodologies.

FOR YEARS, THE DIGITAL CHIP DOMINATED industries from automotive to aerospace. But lately the revolution in high-bandwidth communications technologies has led to a sharp increase in the use of analog/mixed signal (A/MS) chips. Demand for A/MS chips is expected to grow by 25 percent in the next few years, so engineers need to shift their technology paradigms to meet the challenges ahead.

The growing design complexities make it imperative for designers to use the newest analog HDLs for top-down analysis while retaining the bottom-up analysis of the transistor level. The discontinuity evident here is that analog and digital designers both need to move rapidly to adopt these languages in order to accurately create and test these new designs. For example, digital designers who need to incorporate some analog components into mixed digital/analog designs will find that using languages such as VHDL-AMS or Verilog-A is less of a challenging learning curve than trying to incorporate traditional analog methodologies. To become truly competitive in this fast-paced segment, designers will be required to make the transition to top-down design techniques that take into account the needs of digital and analog designers alike from the beginning of the design.

Discontinuities occur when existing tools stop working. Traditional schematics are no longer useful with today's large and complex designs. Leading-edge companies have begun to make the transition from traditional analog tools to using next-generation analog HDLs such as Verilog-A and VHDL-AMS. These tools have been around for a few years, but it is often more difficult to train people than it is to create new software, so the industry as a whole has been slow to adopt them. Both the learning curve and the initial capital investment can be a stretch. However, as this market continues to grow, the individual design engineers who have the foresight to increase their skills and the businesses that have the vision to plan for the future will outperform their competitors.

There are many strong business reasons that should compel analog and digital designers working in the A/MS space to make the switch to top-down design using the newest developments in HDLs. Ever-increasing chip complexity and time-to-market pressures continue to stretch our current SOC development techniques. System-level design, especially mixed signal design and partitioning, is a major cause of schedule delays. The size of today's analog designs makes it impossible for an engineer to go straight from specification to transistor-level design. Designers need to increase their productivity. Utilizing top-down design with the new analog HDLs allows them to accomplish this.

For example, many engineers are trying to implement analog features in low-cost digital CMOS chips. Typically, analog and digital subsystems are created separately, do not interact until IC layout and remain untested until fabrication. Any faulty interaction found at this point can result in expensive production delays and possibly in lost market opportunities. Fortunately, there are now tools available that support behavior modeling and standard analog modeling languages as well as mixed signal verification. Key solutions filling the gap include behavioral model libraries, the analog HDLs already mentioned and design simulators.

Behavioral libraries mimic the behavior of a device and can be implemented at several levels of abstraction. Examples range from a simple op amp to a complex multipole zero op amp. Each model also offers dozens of parameters to enable virtually unlimited customization. If a model is not available to describe a proprietary design, a designer can use an analog HDL such as VHDL-AMS to create new models or write custom code.

The current trend toward joint partnerships and purchased intellectual property makes it important to use a simulator that accepts all standard HDLs, including Verilog, Verilog-AMS, VHDL, VHDL-AMS, SPICE and C-level models. Language-independent simulators allow designers to reuse major portions of the analog or digital test bench in the full-chip verification. The models created for this design and refined for the verification are also ideal starting models for the next generation of the product. The models also improve and mature along with each generation.

Designers facing the prospect of complex mixed signal chips should consider their own willingness to make radical shifts when necessary as they plan for the future. With continued acceptance and use of the new A/MS tools, we will soon find that we have successfully traversed this discontinuity in analog/mixed signal design and moved on to the next challenge. Even better, a whole set of engineers will be even more indispensable to their employers because they have mastered another design challenge.