A Case for Merchant-Market OC-192 Silicon

Electronic News, June 4, 2001 by Bidyut Parruck

IN BUILDING HIGH-SPEED switches and routers, designers have traditionally developed their own ASICs for key parts of the data path, including traffic management, packet classification and switch fabrics. Because of a number of new challenges in building the emerging generation of OC-192 routers and switches, the development of in-house ASICs for this equipment is much more risky than using slower-speed ASICs. In addition, changing market dynamics have reduced the rewards of in-house ASIC development. After assessing these factors, equipment vendors are concluding that the preferred approach for building and upgrading OC-192 equipment is to use merchant-market silicon.

Next-generation fiber optics equipment also presents a number of new challenges to system designers. First, the performance demands of equipment for OC-192 have quadrupled or more. These speed challenges are further increased by the rapidly escalating number of wavelengths in dense wavelength division multiplexing (DWDM) systems and by the desire of carriers for a single box to terminate one or more DWDM links.

To accommodate faster bit rates, the input and output buses of data-path chips must become wider and faster. The memories used for packet storage must become deeper, wider and faster to allow for the handling of more data and larger buffers. In order to manage all these high-speed buses, it's necessary to use sophisticated packaging approaches that handle more than a thousand pins, many hundreds of which operate at hundreds of megahertz. Flipchip packaging is generally required to manage the I/O count and signal speeds, as wirebond packages can handle neither the I/O count nor the signal speeds. In many cases, advanced communications chips have more high-speed I/Os than the industry's fastest microprocessors, placing onerous demands on power-supply decoupling and ground-bounce prevention. As a result, the designers of these chips must model signal integrity from the chip, through the package, and into the surrounding components on the board.

Equipment designers are also faced with the challenge that the convergence of traditional telecom and datacom infrastructures is creating multiprotocol traffic with a range of quality-of-service (QoS) requirements. Carriers are demanding multiprotocol, QoS-enabled boxes in order to let them adjust to unpredictable changes in traffic mix immediately, using software as opposed to the traditional approach of swapping single-protocol boxes. Multiprotocol boxes allow carriers to future-proof their infrastructure against changes in traffic mix.

Chips with multiprotocol and QoS capabilities require much more complex logic than singleprotocol chips. The risk of a chip not operating properly increases with the number of different protocols and QoS levels it must manage. Managing this risk requires more detailed simulation, comprehensive verification of the logic in an FGPA-based prototype and more exhaustive validation of the first silicon. A merchant semiconductor vendor can amortize these increased costs across its customer base, whereas a systems company can only amortize these costs over a relatively small number of boxes.

Carriers want to create new billing models around different enhanced service classes, creating a need for extensive statistics gathering in each communications node -- another challenge for the designer. In some cases, this requires tracking as many as one million separate flows. This further increases design complexity and risk, both from a logic standpoint and in providing the memory structures and throughput to track data for up to one million flows.

Financial considerations also pose a challenge. With the recent economic slowdown, equipment OEMs are competing in a tighter market. Time-to-market becomes increasingly important. The use of merchant silicon is generally a much faster path to equipment production than the risky in-house development of ASICs.

For an equipment vendor contemplating an in-house development, the above risks argue against in-house ASIC developments. Of course, if the rewards of in-house development were substantial, then perhaps assuming these risks would make sense. However, in today's marketplace, with high-speed merchant silicon arriving, the rewards of in-house ASIC development are shrinking, not growing.

Standards are part of the reason that in-house development rewards are shrinking. Over the last few years, both the Optical Interworking Forum and the Network Processing Forum--a combination of the CSIX and CPIX standards groups--have provided both hardware and software standards that allow best-of-breed merchant silicon solutions to be used together by equipment vendors.

Fueled by these standards, a merchant-market OC-192 silicon for traffic management, packet classification and switch fabrics will soon be available.

Equipment vendors need a way to differentiate their products, especially if they all use the same merchant silicon suppliers. Higher-level software is an excellent way to provide this differentiation. With the trend toward multiprotocol, multi-QoS equipment, rich opportunities to differentiate equipment in high-level software exist. The Network Processing Forum's standardization work on software APIs allows equipment developers to create high-level software that will operate with any standards-compliant merchant silicon. The emergence of these API standards allows equipment designer to use their software through successive generations of equipment, thereby providing a longer-living asset than a single generation, in-house chip design.