2001 Ad

Electronic News, June 4, 2001 by Sang Wang

Santa Clara, Calif.

THE DESIGN AUTOMAtion Conference (DAC) is almost upon us. As a lead-in to DAC 2001, let me survey and comment on where we've come since June 2000 and what to look for as we head into this year's conference.

With "embedded systems" as the catchphrase for this year's show, it's notable to see how this potentially startling shift in focus--for DAC attendees--is actually a natural continuation of what came out of last year's DAC. Is DAC turning into a software-development-oriented event? Has DAC lost its hardware-design focus? Of course not.

Rather, DAC 2001, to be held June 18-22 in Las Vegas, is quite saliently recognizing the increasing prominence of one subset of embedded systems: semiconductor intellectual property (IP) and its remarkable effect on design flows, tool capability and tool capacity. In the space of a year, the industry has seen IP move from a good idea that has a lot of issues to contend with to the spur of the next great shift in chip design methodology. In fact, attendees might want to give this year's DAC a subtheme and say that this is the year of the realization of actual system-on-a-chip (SOC) design. This year's conference might even be remembered as the IP DAC.

DAC 2000 set the conceptual stage for SOC design, a design trend that the EDA industry talked about a lot, but a methodology that users had not implemented en masse. In my DAC 2000 post-mortem last year (Electronic News, June 12,2000), I noted that several technological issues would have to be resolved for us to more effectively realize SOC design. Where are we on these issues?

Physical compilation/timing and design closure--Certainly a facet that's still in market-adoption mode. A number of aggressive vendors in this area--both established and start-up - are in missionary mode. Some level of success has been achieved, but we are still some distance away from significantly reaching maturity and impacting global designs.

Verification--Users are starting to make the leap to full-chip, high-speed, highly accurate circuit simulation and analysis, which is critical if we want to see SOCs get to silicon success in a consistent fashion. Functional verification needs to become more efficient in handling larger and larger designs as well as including mixed signal in verification.

System-level languages -- This area continues to search for convergence. We have a host of proprietary languages and tools with no clear standards path for users to follow. Nevertheless, it is of high importance to achieve convergence for more effective system specification, design and communication.

The dot.com-ing of EDA--Certainly, we aren't going to see a revolutionary change in the way we design, as some people thought last year. It's evident now that big companies don't want to risk compromising their SOC design security by designing on the Web. The vaunted application service provider (ASP) model hasn't enjoyed astounding success. Small design houses may be the EDA ASP's primary customers.

As was the case last year, networking and communications, both wired and wireless, and futuristic, Star Trek-type consumer products are driving SOC designs. EDA users will be looking for tools and technologies to design and verify 20-million-gate chips, with on-chip memory blocks, a number of analog/mixed signal components as well as processor, DSP or MPEG IP. Any new tools or solutions that can help designers to meet this tough challenge will be highly interesting and looked for by users. Other drivers include microprocessors with speeds approaching 2GHz, wireless devices operating in the multiple-gigahertz range and networking switching at and above 10GHz speeds. Process technologies are going to go down to 0.13 micron and continue to move toward 0.10 micron and below. We also are noticing a clear shift to programmable design as FPGAs continue to grow larger and faster, and allow more on-chip memory and processor design-in, via semiconductor IP.

In other words, DAC 2001 will compel us to take a look at which technological forces will make SOC design actually happen as we begin seeing users work on complex designs of up to 20 million gates on-chip, with dozens of embedded cores, and sending them to silicon.

What technology will this take, and will we see it at DAC 2001? Timing and power issues obviously continue to be nontrivial challenges. Users are saying that they need to get a handle on timing and power characterization. Verification, especially in the post-layout segment, continues to require increased capacity, speed and accuracy. Nanometer effects must be accounted for as integral parts in the SOC designs of today and tomorrow. Finally, more analog and mixed signal capabilities will need to be apparent as more and more SOCs process mixed signal data.

From a business perspective, watch for EDA vendors going public in this supposedly dismal economy. What's the key? Differentiated, star-quality technology. The four IPOs since DAC 2000 have been quite successful. Of course, any EDA company planning to go public will have to provide good value to design or verify IP-laden SOC designs.