A Big Slice of SP&R Pie

Electronic News, June 4, 2001 by Gale Morrison

Barbarians gather at Cadence, Synopsys gates

RESEARCH TRIANGLE PARK, N.C.-- The global semiconductor market may be in a big slump this summer, but the dozen or so EDA companies working in next-generation IC design know an opportunity when they see it. Any company hoping to design ICs at 0.13 micron has to buy into the next-generation of EDA tools, and in recent years this has emboldened several start-ups to come up with alternatives to the big players and lure these customers away.

It's all happening because this year the semiconductor industry is deep into one of those only-once-in-a-decade design-inflection points.

Design size and complexity forced EDA providers to come up with a whole new way of designing chips: the merging of logic synthesis, the front-end, with placement and routing, the backend. Synopsys Inc., Mountain View, Calif., dominates the former; Cadence Design Systems Inc. of San Jose just holds a majority share in the latter over Avant! Corp. of Fremont, Calif. All three companies, though mainly Synopsys (nasdaq: SNPS) and Cadence (nyse: CDN), have engineered new physical--synthesis offerings to support their customers' needs and to keep their dollars coming.

According to San Jose-based research company Gartner Dataquest estimates, the two segments, register transfer level (RTL) synthesis and IC place and route, combined should equal software revenues of around $666 million this year.

Unfortunately for the big players, companies such as Magma Design Automation, Monterey Design Systems (which this spring bought fellow crusader Aristo Technology), Silicon Perspective, and Get2Chip have spent the last two to three years preparing for this opportunity. Now they are heading to the Design Automation Conference (DAC) 2001 in Las Vegas (June 18-21) with even more ambitious products, more sales executives, more customer successes and more venture capital to get it all done. They want some of Cadence, Synopsys and Avant!'s market share, and they want it bad.

Today, Monterey Design Systems Inc. will announce partnering with Synplicity Inc., San Jose, to bring Synplicity's RTL synthesis into its offering. It's a bold move for the Sunnyvale, Calif., start-up, as it bypasses Synopsys synthesis, which by most estimates 85 percent to 90 percent of IC designers use. Fortunately for Monterey, Synplicity (nasdaq: SYNP) went public last fall and has access to lots of capital in order to support its customers.

Also today, Cupertino, Calif.based Magma is launching Blast Logic, a product that reads in a netlist, and constraints and generates reports that, according to the company, logic designers use to better assess the timing feasibility of their design before hand-off to layout.

To entice customers away from Synopsys and Cadence, Magma is bundling its RTL synthesis capability-Blast RTL-with Blast Logic. Licensees of Blast Logic can receive a free, one-year upgrade to Blast RTL.

Magma said customers were clamoring for a tool to assess timing before going through synthesis. (Competitor and possible cooperator Get 2 Chip Inc., Santa Clara, Calif., also offers this in addition to its alternative to Synopsys synthesis.)

"Our customers consistently tell us they place a high value on our system's unique ability to deliver timing information prior to physical design," said Bob Smith, vice president of marketing and business development at Magma. "Based on this positive feedback and several requests, we developed Blast Logic so that logic designers can now get better visibility into their design's post-layout timing."

These moves are only the tip of the physical-synthesis competitive iceberg. On June 11, the start of the final week before DAC, Magma and Get2Chip will announce even more ambitious plans than these, and Silicon Perspective will begin talking about its latest developments. And don't expect Synopsys, Cadence and Avant! to take that lying down.