Assertions come into their own: design technique makes mainstream debut at DAC 2002 - News - Design Automation Conference 2002

Electronic News, June 10, 2002 by Gale Morrison

Some of the biggest news in functional verification at this week's Design Automation Conference (DAC) in New Orleans is the wholesale assimilation of verification "assertions" by Synopsys Inc. and Cadence Design Systems Inc. Both companies have committed to rolling assertions into their mainstream simulation and formal verification environments.

Assertions have surely hit the mainstream when the two biggest EDA companies in the world are placing them firmly in the center of their functional verification offerings. Assertions are statements within the RTL that mandate behavior. In this way, a designer can decree that the logic does not, in essence, step outside its bounds and cause a problem. The sheer complexity of ever-larger designs and the increasing presence of third-party IP within them has prodded design engineers to get to know and love this technique.

As the downturn continues and design budgets get continually squeezed, though, the question is whether the smaller, independent companies at the forefront of functional verification for at least the last three years--the Zero-In's, the Real Intents, the Verplex's, the Averants--will shortly see all of their evangelizing and standards process participation flatly co-opted, without even a big buyout check to show for it.

With Cadence and Synopsys' sizable clout and marketing muscle, functional verification using assertions will roll out to the masses according to their vision, which calls, they say, for adoption that's as easy as possible and via tools users already know. "The adoption of assertions first from a dynamic simulation point of view, and then, after that, from a standard static timing analysis methodology point of view will enable the mainstream design community to ease the adoption curve," said Mike O'Reilly, VP of systems and functional verification at Cadence. Cadence is going to have assertions based on the Sugar language adopted by Accellera, which will be out by the fall.

Synopsys last week said that the upcoming VCS 7.0 will welcome assertion-based verification. "We are redefining VCS from HDL simulation to being a platform for smart verification," said Farhad Hyat, VP of marketing for the Verification Technology group of Synopsys. "VCS is going to be the operating system for verification."

Synopsys and Cadence have a powerful argument in promising to make the use of assertions easier. Even with the standardization efforts this spring, the technique is complex. It's been the domain of the highest echelons of design for some time and still calls for the use of unique verification language that's just barely entering wide circulation. But executives say these obstacles can and should be surmounted.

Dino Caporossi, VP of marketing at formal verification player Verplex, says assertions are useful for everybody, not just the power-users. "A wide variety of users will find it useful. Not just communications. All engineers have to check a hand-shake signal, for instance," said Caporossi, "though, it really depends on which level of assertions. For instance, SGI, which is one of our customers, uses more complex assertions because they have ECC (error-correcting circuitry) th is very complex and must be verified to a greater degree than most circuitry."

But Caporossi emphasizes that assertions are but one piece of the puzzle. "You need every verification means at your disposal," he said.

He quickly added that customers find assertions especially helpful. "Customers claim that by using assertions they can get to a stable model (aka golden RTL) more quickly because you are running assertions really early on at the RTL level and finding detailed bugs. By finding more detailed bugs sooner, you lessen the chance that a downstream bug will be found. And downstream bugs are especially nefarious because you have to redo so many design steps when you find them.

"Assertions and formal verifications are added insurance against respins," Caporossi said.

However, Co-Design Automation, the backers of Superlog and several tools for it, contend that without a common and single standard language, real improvement in the verification time-and-money drain won't come. And Co-Design, in saying so, is not only out to sell more product. Superlog has been winning accolades among the E-mail Synopsys Users Group set, and it's being melded into System Verilog, version 3.0 of which just won approval by the Accellera board last week.

Dave Kelf, VP of worldwide marketing at Co-Design, said that if EDA can come together on one language for design and verification, even better methodology improvements are in store. "Even more interesting are the methodology improvements that can be obtained by combining semiformal and formal techniques, with simulation coupled to test-bench generators," Kelf said. "This can be accomplished using a common language structure to drive all of these tools. Assertions are key in enabling a cohesive methodology across these tools.

"If a standard assertion language can be created that operates across several tools, methodologies can be constructed more easily that bring these tools to bear on single verification problems, increasing functional coverage and productivity dramatically," he said. Perhaps the company that brings this change to bear will be the one to get financially rewarded and win widespread adoption.