Custom FPGA-Based Emulators Accelerate IC Design Verification

Electronic News, June 19, 2000 by Ray Turner

Another critical improvement is that custom FPGAs developed for emulation have a very high pin-count relative to the number of gates. The new design uses a hardware-based two-to-one I/O multiplexer ring around a sea of configurable logic blocks that doubles the effective pin-count more than tripling the number of usable gates. These features increase the effective capacity of a system built with custom FPGAs to 20 million ASIC gates.

The use of custom FPGAs also makes it possible to build a hardware-based logic analyzer, a feature that consumes precious resources of off-the-shelf FPGAs. It consists of a matrix of switches that makes it possible to record any signals in the circuit being emulated including I/O. At any point in time, emulators built with custom FPGAs can determine the current state of every signal in the entire design being tested. With the logic analyzer built into the FPGA, designers can move probes instantly, avoiding lengthy delays for compiling probes. The switch matrix can reassign signals to pins at run time, eliminating what is usually the most time-consuming step of the debugging process.

When you perform emulation, you have to slow down the real world to the speed of the emulator. This is not normally a problem but there is a limit beyond which anomalies begin to occur that make it impossible to accurately emulate a device. The use of custom FPGA's makes it possible to increase the speed of the logic analyzer to 2MHz while still providing 100 percent visibility. This level of speed provides an accurate emulation of virtually any device, eliminating a limitation of generic FPGAs and making it practical to provide 100 percent internal visibility on every emulation. The result is a substantial improvement in debugging productivity.

The use of custom FPGAs also makes it possible to build in the capability to set, force and release any storage element such as a flip-flop or register without compiling. The ability to perform these functions without this delay can significantly increase the speed of the debugging process. During debugging, designers frequently have a hunch of what is causing a problem and need a way to confirm it. The best way is usually to force signal values to change in the same way the proposed fix would. This is much faster than actually changing the design to model a proposed solution to the problem. Instead of adding a gate to turn off a signal at a certain time, you simply run the emulator to that point and force the signal to zero to see whether that really fixes the problem. The fact that custom FPGA-based in-circuit emulators can perform this task in a few minutes rather than a half hour significantly increases the speed of the debugging process.

The inclusion of a complete logic analyzer with instant probe changes, event detectors and pin multiplexing means that designers can move probes instantly, avoiding lengthy delays for recompiling probes. The usual limitations of providing 100 percent internal visibility in terms of sampling frequency, depth and capacity are eliminated. Several other improvements are also simultaneously reaching emulators that are not directly related to the use of custom FPGAs.