Synopsys Prepping Mixed Signal Play?

Electronic News, June 18, 2001

WITH THE ANNOUNCEMENT TODAY OF THE FINAL CLOCK-TREE synthesis and routing pieces of Synopsys Inc.'s RTL-to GDSII IC design flow (see story, page one), there can be no mistaking the breadth of the competition between Synopsys (nas daq: SNPS) and Cadence Design Systems Inc. But Dave DeMaria, Cadence's (nyse: CDN) senior vice president of worldwide marketing, said Synopsys still hasn't done enough.

While the two might compete more than ever for what Gary Smith at San Jose-based Gartner Dataquest calls the available IC implementation dollars, DeMaria contends that Synopsys has no answer for the time fast approaching when all system-on a-chip (SOC) design is mixed signal design. Consensus across the semiconductor industry is that communications, wired or wireless, is a must for every new SOC, and that means an analog component. Synopsys has not discussed with the press or analyst community any plans to field mixed signal design technology. But at least one analyst believes the company has got this issue under control, and that Cadence is right about the opportunity in mixed-signal SOC design. "I think they are preparing some thing," said John Barr, senior analyst at Robertson Stephens in New York. "I think deep within Synopsys there's analog expertise that could come out. Nothing has been disclosed to me, but I think they do. And (mixed signal SOC design) is a major opportunity as we look out a couple of years."