Going Formal Dresses SOCs for Success

Electronic News, June 18, 2001 by C. Michael Chang

What accounts for the success of breakthrough EDA technologies such as formal verification even as the overall electronics industry stumbles a bit? Simply this: Tools or methods that solve fundamental problems, often by redefining or reinterpreting a problem, will always find eager buyers waiting to snap them up.

And so it is with verification of large, complex systems-on-chips (SOCs), many containing 10 million or more transistors. Simulation has long been relied upon for verification but the increasing complexity and sheer scale of today's SOCs makes it nearly impossible to rely on simulation alone. Using even partial vector sets, simulation often simply takes too long for each iteration, giving designers an unpalatable choice: stretch out the design cycle by running enough vectors to be comfortable or risk missing logic errors by verifying less thoroughly. Most err on the side of caution. In fact, current estimates are that when relying solely on simulation, 70 percent of the design cycle is burned up on verification.

The reality is that simulation alone is inadequate for verifying SOC designs because performance is slow and coverage is incomplete. Even worse, as designs continue to grow, simulation vectors will increase exponentially. On the other hand, formal verification is faster than simulation, requires no vectors and is exhaustive in ensuring more bugs are caught earlier when they are much easier to fix.

As SOC complexity and density rise, faster and more thorough verification becomes ever more important. Electronics companies world wide have found that an intelligent verification strategy is critical to meeting their design objectives and time-to-market requirements. Once thought of as early adopter technology, formal verification is fast becoming a relied-upon productivity booster and key strategic weapon.

Formal methods offer the designer a much more intelligent path to SOC verification. Rather than applying stimuli to a design and comparing its responses with expected results, formal verification studies a circuit to mathematically prove or disprove its functional properties. The huge effort needed to create functional test vectors can be avoided except for those parts of the design where simulation makes sense, and a thorough verification can be achieved in a much shorter time than using simulation. Unlike simulation, which only shows the presence of bugs, formal verification can prove their absence. When errors are found, formal verification tools automatically generate counter examples to demonstrate the error conditions. This enables designers to complete verification tasks faster and with a much higher level of confidence.

Formal verification tools can be valuable throughout the design process. In the creation stage, they will demonstrate if a design satisfies certain desirable properties and can derive functional vectors to demonstrate the violation of such conditions.

Formal verification is also a tremendous help when assembling multiple blocks from different design teams into an SOC because it does not require everyone to have detailed knowledge of all other blocks of the chip. Instead, each designer can focus upon verifying interface constraints that are specific to their own blocks.

After a higher-level model is created, a design usually has to go through several stages such as test logic insertion and clock-tree synthesis--formal verification can be useful here too. Late in the design cycle, it is often necessary to tweak the logic to correct timing problems after layout. During these design iteration and revision steps, a formal equivalence checker can compare two designs and make sure no errors were introduced.

It is becoming clear that formal verification offers tremendous return on investment (ROI) by eliminating time-wasting drudgery while simultaneously delivering better quality results. By doing so, it lets design teams concentrate on what they do best, namely, create killer intellectual property, instead of dissipating precious resources.

C. Michael Chang is the president and CEO at Verplex Systems Inc. based in Milpitas, Calif.