2001 Ad

Electronic News, June 18, 2001 by Roy Jewell

As we head into the 38th Design Automation Conference (DAC), I expect we'll see a variety of new and improved EDA tools, all claiming to help chip designers shorten time-to-market pressures while increasing their productivity. Some will be clear winners, others will be also-rans, while still others will miss the mark entirely.

The aisles will be filled with designers whose companies have experienced rapid growth driven by the increasing demand for faster, more compact and power-efficient electronic products. These designers continue to feel the pain--even during this economic slowdown--as competition and innovation continue to force a shortened product life cycle, making time-to-market crucial to a product's success.

Market pressure has accelerated the trend toward deep-submicron (DSM) design where feature sizes are 0.18 micron or less. DSM processes allow the production of complex chips containing millions of gates. This has allowed system-on-a-chip (SOC) devices that integrate multiple functions on a single chip and offer significant performance, cost and power advantages over systems that require multiple ICs to perform the same task.

Trends toward DSM and SOC designs have driven demand for improved EDA software, while the EDA industry has been accused of not keeping pace. Limitations in EDA technology have been blamed for slow adoption of DSM processes.

Let's look at the evolution of the EDA industry to understand why. Historically, EDA companies developed software for use by separate engineering groups to address either the front-end chip design or back-end chip implementation processes.

In the front-end process, the chip design is conceptualized and written as a register transfer level (RTL) file that describes the required functionality of the chip. For large chips, the design is often divided into a number of individual blocks, each with its own associated RTL file. This is often done because of capacity limitations in existing tools. Designers develop constraints for the design that are used to describe the desired timing performance.

A target library is specified that contains detailed information about the basic functional building blocks, or logic gates, that will be used in the design. The next step is to run the RTL files through synthesis software that generates a netlist. The netlist describes the circuit in terms of logic gates selected from the target library and connected such that the functionality specified in the RTL files is realized. Synthesis performs optimizations to attempt to meet timing constraints specified by the designer.

After the layout is completed, the final step in the back-end process is to run timing analysis to verify that the chip will run at the desired circuit speed. If circuit speeds are slower than speeds reported by the synthesis software, the design is often iterated back through synthesis again in an attempt to improve timing. Since each timing-closure iteration cycle can take one or more weeks, successive iterations of the design process can delay time-to-market for new chips.

The trend toward DSM technology has rendered traditionally separate front-end and back-end EDA processes less effective. As ICs have increased in complexity and feature sizes have dropped, problems faced by chip designers have changed. Wire delay now accounts for the majority of total circuit delay and has become the most significant factor in circuit performance. Front-end estimates of wire delay may vary from actual wire delays measured in the final layout.

DSM process technologies bring additional complexities to the design and implementation process. Using existing design flows and software, designers must contend with analyzing and fixing these problems manually after the layout is completed. These adjustments often change the chip timing and further contribute to the timing-closure problem.

These challenges make it difficult to efficiently design chips using separate front-end and back-end processes. Semiconductor manufacturers and electronic products companies are seeking alternatives to older-generation EDA software. As a result, an opportunity exists for a new approach that will allow the design of more complex ICs, improve performance and reduce time-to-market for next-generation electronic products.

Roy Jewell is the president and COO at Magma Design Automation Inc., based in Cupertino, Calif.