ARC Debuts Instruction-Set Architecture for Cores

Electronic News, June 18, 2001

U.K. PROCESSOR DEVELOPER ARC CORES OF ELSTREE, ENGland, has announced an instruction-set architecture (ISA) that it claims allows designers to mix 16-bit and 32-bit instructions on its 32-bit user-configurable processor. The report comes from Electronics Weekly, a sister publication to Electronic News.

The main features of the ARCompact ISA include 32-bit instructions designed to provide better code density, a set of 16-bit instructions for the most commonly used operations and freeform mixing of 16-bit and 32-bit instructions without a mode switch. "The new instruction set expands the number of custom extension instructions that customers can add to the base-case ARCtangent processor instruction set," said Phil Barnard, the product manager responsible for ARCompact.

"The existing processor architecture already allows customers to add as many as 69 new instructions to speed up critical routines and algorithms," Barnard said. "With the new ISA, customers can add as many as 256 new instructions." According to Barnard, with 32-bit architectures becoming more widely used in embedded system designs, code density can have a direct impact on system cost. "Typically, up to 90 percent of the silicon area of a system-on-a-chip is taken up by memory," Barnard said.