Cadence plans to best competition: serious changes in product strategy come into focus - Design Strategies

Electronic News, June 17, 2002 by Gale Morrison

The serious changes in product strategy and senior management that have been going on within Cadence Design Systems Inc. over the last year and a half came into sharper focus last week when the company played host to press and analysts to kick-off the Design and Automation Conference (DAC) in New Orleans.

"About 18 months ago, I decided that Cadence needed to make some changes," said Ray Bingham, the San Jose-based company's CEO. "And I identified Lavi Lev as the person to help me do that."

Lev, executive VP and general manager of Cadence's IC Solutions business, joined Cadence about a year ago. Lev is a former Israeli Defense Forces paratrooper and was previously a chip designer for Intel, MIPS Technologies and Sun. Lev was very frank last week in his opinions of what goes wrong in EDA and what had been going wrong at Cadence--something he learned the hard way as an EDA customer, he said.

"I found myself looking at a collection of design tools designed by people who had never designed a chip before," Lev said, "and an EDA industry more concentrated on hurting each other than helping me."

Lev said this was evident inside Cadence, too, and the company has made tough decisions in its attempt to remedy that.

"We started a ruthless process of looking at the product line and figuring out what and who was needed to move ahead," Lev said. A number of decisions came out of that process, he said, but one of the most important was identifying the key technologies for IC design.

"Routing, virtual prototyping and physics are the key to modem design," Lev said.

To that end, Cadence ended the Integration Ensemble (IE) program, which was to be its next-generation routing, or back-end, tools, and reached out and grabbed Silicon Perspective Corp. and Plato Design Systems, among a couple of other acquisitions.

"LE was a good program," Lev said. "But it was not enough. We revamped that program and created SOC Encounter." Lev said it was not an easy call to make.

"On IE, we had to take a pretty ruthless view," he said. "It was a good product for 0.13 micron, but we needed something that would take off there and keep going. We didn't want to have a tool out there that worked for 0.13 micron and started having problems at 90nm."

Lev said new management was a big part of that process.

"Over the last year or so we've gone out and cherry-picked the best technologies and built up the best team [of executives] ever assembled under one roof."

He called out Ping Chao, who came to Cadence with Silicon Perspective, a couple of times; and also Steve Teig from Simplex; Limin He from Plato; and Charlie Huang from CadMOS.

Throughout the speeches last week Cadence alluded to the newly combined Synopsys-A vant! and sought to downplay any notion that the merged company would be bigger than Cadence. But toward the end of his presentation, Lev went off script and gave his opinion of their new competitive flow.

"Here I want to say something about that," Lev said. "Aart [de Geus, head of Synopsys] is taking the best front-end tools and the best back-end tools for 0.13 micron. This gives them tools ready for what we were doing two years ago.

"You can't push together the front-end and the back-end and think it will work," he said. "Modern design flows have no ends." Chips, packages and hoards going forward must design and verified simultaneously, he said.

Lev was asked later if Cadence's SPC could stand up to the threat from Synopsys' Hidden Dragon hierarchical planning tool, which the company introduced last week.

"SPC has had 250 successful tapeouts," Lev said. "Hidden Dragon is a bunch of foils."

Lev emphasized several times that more cohesive and concurrent engineering is required below 0.13 micron, with a much greater concentration on manufacturing and packaging issues. Later in the presentation, Dave De Maria, worldwide sales and marketing head, said Cadence would be introducing a chip I/O planning technology in the second half of this year.

Lev gave competitor Mentor Graphics some credit on the design rule checking (DRC) and physical verification front, but indicated Cadence intends to change that dynamic.

"We are unhappy about our position in DRC. I have to say that Mentor did a good job with Calibre," Lev said. Cadence intends to "get much deeper into the fab," especially now that the company has hired Marc Levitt, formerly of Transmeta and Sun, as VP of its new design for manufacturing unit.

Finally, Lev said Cadence is sure it can best its competitors in custom IC design, especially the concurrent and optimal design of analog and digital circuitry.

"Cadence has committed itself for 10 years to this problem, and for analog it's a very, very nasty problem," Lev said. He said the company has been able to greatly simplify and automate mixed signal design, and he does not think Synopsys can approach them in this area.

"Synopsys does not have analog capability," Lev said. "They've made their first embryonic step with the Avant! HSpice tool, which measures waveforms. That's like the ability to take the temperature of a cake. It tells you nothing about the recipe or how you are going to actually make it."