Market pressure drives new semi development - Comment

Electronic News, June 17, 2002 by Simon Young

DESPITE INCREASING complexity in semiconductor design and manufacturing, many companies approach IC development with traditional views of semiconductor product life cycles.

Accordingly, manufacturers risk additional silicon spins in anticipation of extended revenue under old assumptions about the balance between risk and reward.

In today's environment, the combination of increased product complexity and dramatically shorter product shelf life has changed the profit equation. What's more, the chance of silicon failure is high, adding further pressure to companies' product development strategies.

Today, revenue success is tied closely to early silicon success. To maximize return, semiconductor companies need to move toward a more reliable model for product development. In this environment, companies need to consider new risk factors that impact profitability and affect the balance of risk/reward in semiconductor development flows.

For every semiconductor development project, the fixed costs for systems, tools and training combine with significant variable costs. These costs push new product programs deep in the red well before the first sample leaves the factory. Yet, quick time-to-market at sample volumes is essential for design wins, and design wins are necessary for the real prize--high-volume delivery and revenue sustained well after all costs are recovered.

Unfortunately, two key changes in the semiconductor industry have disturbed this traditional formula for success: Companies can no longer rely on sustained delivery to fill cash coffers; instead, shorter product shelf life means they must hit breakeven more quickly than ever and rely on product functionality and performance to fetch a premium price that can accelerate the rate of return. Unfortunately, the other significant industry change works against the need for faster time-to-market and quicker breakeven: Design complexity has extended development, deepening the burn rate among engineers, who increasingly face tapeout with little confidence that they can deliver first-time correct silicon on schedule.

In moving to advanced nanometer process technologies of l50nm and below, semiconductor designers find themselves facing an array of new challenges. At nanometer geometries, subtle electrical and physical phenomena introduce significant coupling, crosstalk noise and other effects that can dominate performance and timing. Because of the sheer complexity of analysis required to uncover these potent nanometer effects, traditional gate-level and SPICE-based verification methods break down for leading edge designs. Newer approaches for hierarchical post-layout analysis provide the needed speed, capacity and accuracy to uncover nanometer effects. Furthermore, this type of detailed analysis enables engineers to optimize nanometer designs for greater performance and yield.

Yet, some design groups shy away from more sophisticated analysis methods, influenced by traditional development philosophies that emphasize the quickest path to silicon, regardless of the risks. Others simply lack the necessary tools for dealing with nanometer effects. Not surprisingly, the industry now finds itself facing the harsh fact that more than 50 percent of nanometer designs actually require two or more respins to achieve correct silicon.

With older development philosophies and technologies, companies could expect preventative measures to account for design uncertainties, and those problems that did slip by could be handled in the next silicon spin. Both the risk and the cost of failure, though not insubstantial, were acceptable. With nanometer designs, however, companies face a harsher reality. Even as the likelihood of failure continues to increase, the cost of failure is skyrocketing, for example, mask sets for emerging semiconductor processes are quickly approaching the million-dollar mark.

Because silicon failure is so devastatmg in terms of both real costs and opportunity costs, leading semiconductor companies are recognizing that the shortest path to success might not be the quickest path through design. Rather than seeking shortcuts to silicon, nanometer designers are finding that extra effort in detailed analysis and solid engineering offers the best insurance against silicon failure and costly respins. In the face of increasing cost pressures and design complexity, companies able to refocus on improved analysis will not only achieve faster time-to-market but also faster time-to-profit with more competitive ICs.

Simon Young is the product line manager for Nassda Corp. Please contact him at spike@nassda.com