ARC to integrate Synopsys' technology - Core Concepts

Electronic News, June 17, 2002 by Peter Brown

ARC INTERNATIONAL HAS INTRODUCED TWO technology developments to integrate Synopsys Inc.'s tools into ARC's design flow. The result of this combination of resources is to speed up development and verification of SOC devices, enabling a much faster time-to-volume production for ARC's cores, ARC said.

The first development involves configurable IP and ensuring that ARC's tools are functioning correctly when designers use different system configurations. By using the Synopsys tools along with the core, designers can test the SOC's processor and peripherals all in advance saving much needed time. The second development is know as RTL Performance Prototyping (RPP), which is said to provide designers with a predictable route to silicon-something handy when moving down to 0.18-micron-and-below design geometries, ARC said.

"ARC believes in providing the best tools for the job to help our customers get their products designed and into volume production fast," said Haig Yaghoobian, senior VP of corporate development at ARC, inn statement. Yaghoobian said that using Synopsys' tools, along with the processors, hardware, software and tools from ARC, will help the company provide their designers with what they need.