Xilinx, IBM tie the knot: next-generation PLD being made IBM ASIC-ready

Electronic News, June 24, 2002 by Gale Morisson

IBM has expanded its design and fab engineering alliance with Xilinx to create hybrid ASICs with embedded Xilinx FPGA cores by 2004, when IBM's 90nm process is in production.

The two companies today will take the wraps off a deal that represents some admission by Xilinx that there is an approaching upper limit to how much silicon real estate OEMs want to own. ASIC mask sets may be approaching $1 million, but with the latest PLDs ringing up at $1,200 to $1,500, the savings of going programmable can erode pretty fast. Altera has been addressing this reality from a different direction with its new HardCopy program, which helps customers move their designs to ASICs once they hit higher volumes.

"Our whole reason for being is flexibility," said Wim Roelandts, Xilinx's president and CEO. "FPGAs are very big die and therefore quite expensive and not suited for volume production.... ASICs are much better in that regard, but they are inflexible. This gives flexibility to ASIC designers. They can build an ASIC but also have a smaller core."

Embedded programmability is a concept that has been bandied about by commercial silicon ven-everyone is familiar to the point of exhaustion with the arguments of "FPGAs vs. ASICs: Who Co-Opts Whom?"

Xilinx already assimilated some part of the ASIC world when it began offering customers IBM PowerPC cores and embraced the use of the IBM CoreConnect bus last year. No. 2 player Altera similarly has mounted embedded ARM and DSP campaigns, which are ongoing. But thus far, embedding programmability into ASICs has proved frustratingly elusive, especially for LSI Logic, which poured years and millions of dollars into its program with startup Adaptive Silicon and then quietly gave up on it earlier this year.

Xilinx and IBM say they have learned from others' mistakes, and this time it can be done.

Roelandts said Xilinx is converging its next-generation stand-alone PLD architecture--due out in 2003--with the specifications required for the Xilinx ASIC core.

"We are already working on next year's generation of PLDs, which we are developing for the 90 nanometer node," Roelandts said. "So what we are doing for IBM is stripping out the unnecessary stuff, such as memory blocks, which ASIC designers get other ways, to make the silicon area as small as possible.

"FPGAs take a large amount of transistors and a large amount of silicon area," Roelandts said. "We are stripping out the unnecessary stuff so the cores take up the least amount of space for IBM ASICs. But the point is this core will be identical to a Xilinx product that will be on the market at that time. ... That reduces the risk for IBM."

Tom Reeves, IBM's VP of ASICs, said the common design rules are key.

"The key enabler is that we already have this foundry manufacturing relationship," Reeves said. "I would have faced a much different task of how do we get a Xilinx FPGA core if everything were on a foreign process."

Roelandts and Reeves said that with the hardware converged, the two can concentrate on the software engineering side, which is what tripped up LSI and Adaptive Silicon.

"There is an expensive amount of software both on the FPGA side and on my side in the standard-cell arena," Reeves said. "Our teams are working very closely on the software side of this strategy. The total compatibility of the process technology made the biggest obstacle on the hardware side go away. Now, the biggest obstacle is on the software side." He added that modifying the test methodology is part of the plan, too.

"I expect it will be very transparent from a process perspective. There are some test strategies that we need to fine-tune and develop," Reeves said. "I will be modifying my test strategy slightly to accommodate the FPGA."

Shelly Davis, VP of marketing at Xilinx, said that only these two can accomplish the broad spectrum of engineering required.

"I've been on this product for awhile now, and I'm extremely excited that we are doing this the right way," Davis said. "We learned from some of the others' mistakes, I think. We're bringing together a very complete product with the silicon, the software, the test methodology, the diagnostic capability. ... All of this has to come together. So far we're doing a very good job of it, and the relationship with IBM is great."

The Xilinx cores will come in 10,000-, 20,000- and 40,000-gate sizes with the capability to integrate several cores on an ASIC and derive a total of perhaps 300,000 programmable logic gates. Reeves said he fully expects customers, who have been asking for this capability for six months, will need "a couple hundred" gates of programmable logic.

Not surprisingly, Altera thinks this a miserable idea.

"What is the upside and what are the opportunity costs?" asked Erik Cleage, senior VP of sales and marketing at Altera. "While I see conceptually why IBM would be interested, I really can't see at all why Xilinx would be interested, These technologies are totally asynchronous with each other. It's not an ideal mix."