Pass That CEO a Pocket Protector

Electronic News, July 2, 2001 by Bernd Braune

SILICON CONTENT TAKES A higher portion of the system bill of materials today than ever before. In fact, it appears inevitable that multimillion-gate systems-on-a-chip (SOCs) will soon become the norm. Just wrap it in an attractive plastic cover, add marketing and ship. All this siliconization is a great thing, but not without risk. If the chip of the future fails, the company touting it could very well fail along with it.

With their reputations and fortunes on the line, then, it is high time for chief executive officers to take a hard look at the role their engineers play in this make-or-break world of IC design. They should be asking themselves: Do we have the necessary design talent to stay competitive? Are we investing appropriately in tools, methodologies, consulting and services? Are we getting a fair return on our investment in all of these areas? Am I asking the right questions?

Things aren't getting simpler, either. Many CEOs running consumer products companies, and even some running high-profile electronics companies, fail to recognize that silicon gets 100 times more dense and complex every 10 years. We have gone from 500-transistor chips at the end of the 1970s to 10 million-transistor chips today. In another 10 years we'll routinely expect engineering staffs to crank out 1 billion-transistor devices.

Keeping up with this kind of change means rethinking how resources are developed and deployed, and retooling to overcome the many technical hurdles. But compare the typical CEO's investment in manufacturing capacity and packaging with the investment in EDA over the last three years. Billion-dollar fabs, yes--but billion-dollar design-tool contracts? Never happened. All too often, engineering brainpower, design capability and intellectual property (IP) creation are looked upon as operational expenses rather than strategic investments.

Sadly, that trend continues as many companies fail to actively adopt new design methodologies. Few have the kind of corporate mechanisms in place to accelerate design innovation or to quickly test and adopt new tools and design techniques -- a costly mistake when one stops to consider that design costs for a 10 million-transistor chip in the SOC era will easily top $400,000 per engineer. Do the math: 25 engineers per SOC at $400,000 a head equals more than $10 million in development costs. Will we still be willing to spend that kind of money for 1 billion transistors?

The need for more complex silicon is clear, and the fact that billion-transistor chips will be on the drawing board very soon is inevitable. SOC design starts of more than 10 million transistors will double every year, and that blistering pace will continue for the foreseeable future.

Historically, every decade has witnessed a fundamentally new approach to chip design that has allowed the electronics revolution to continue. The change this time will be a design transition from the logic to architectural level, requiring new tools and techniques for much bigger transistor counts. The result will be massive productivity gains that come each time the level of design abstraction is raised. In order to realize the full benefits, though, the design community has to pass through a transitory phase before the success is fully achieved.

Changes of this magnitude, requiring both a cultural shift and serious investment, can only come from the executive suite. If you are running an IC design department, pass that CEO of yours a pocket protector; if you are the boss, wear it! A fundamental understanding of the challenges facing designers today is no longer an option for executives, but a necessity.

To be practical, these innovations must deliver immediate, measurable advantages as well as ongoing productivity gains within the first year.

A CEO's best competitive weapon over the next two years will be creative chip designers with application knowledge, advanced design skills, and new and powerful tools. Those who have not invested wisely in their engineering teams, their training and their tools will begin losing design wins to more nimble competitors. And it should go without saying that cutting these operations just to boost margins in the near term is a recipe for disaster. Just remember, there is no need to worry about gross profit if you don't get the business in the first place.

Bernd Braune is the president and chief executive officer at San Jose-based Get2 Chip Inc.