TSMC Selects Ultima's Delay Analysis Tool

Electronic News, July 12, 1999 by Ann Steffora

Ultima Interconnect Technology Inc., Sunnyvale, Calif., will announce today that Taiwan Semiconductor Manufacturing Co. (TSMC) of Hsinchu, Taiwan has selected Ultima's delay analysis tool, Ultima Millennium, as part of its design flows for 0.25-micron and 0.18-micron process technologies.

The Ultima Millennium tool computes interconnect and cell delay data for full-chip timing verification because delay data is critical to uncover timing errors prior to costly fabrication processes, Ultima said. The tool plugs into commercial design flows and uses formats provided by Synopsys Inc., Cadence Design Systems Inc. and Avant! Corp.

"Now that our true 0.25-micron and 0.18-micron process technologies accommodate multimillion gates of system-on-a-chip level integration, our customers need a proven delay analysis methodology that can break the barriers of integration," said Andley Chang, manager of the design services marketing program at TSMC.