Need to Move EDA Tech Spurs Deals

Electronic News, Jan 8, 2001 by Gale Morrison

The two weeks before Christmas saw three EDA mergers (see "Merry Merger," Page 40), and now 2001 has already seen two more. Last Thursday, Cadence Design Systems Inc. said it is buying CadMOS Design Technology Inc.; the same day, Mentor Graphics Corp. said it was buying Speedgate Inc.

The rapid pick-up in EDA mergers, executives said, shows that startups with new EDA technology are fast realizing the difficulty in getting their innovations into the hands of design teams spread around the globe. Many are reluctant to take on more venture capital funding and can see that the IPO market is not a viable option. So, it's team up, or pack-it-up.

San Jose-based Cadence (NYSE: CDN) will immediately begin work integrating its signalintegrity (SI) analysis engines into the Cadence front- and back-end synthesis, place & route (SP&R) design software suites, and into the Assura physical verification and extraction tools, said Paul McLellan, corporate vice president of custom IC products at Cadence. The integrated product should be available by the end of the year, he said.

CadMOS stand-alone tools are available now and already in use at Lucent Technologies, Texas Instruments, Sony, Broadcom, PMCSierra and AMD, among others.

"Signal integrity, for which you need noise-analysis solutions like CadMOS', is the next big problem," McLellan said. "The timing closure problem is largely solved."

Charles Huang, chairman and chief executive officer of CadMOS, said demand from customers for SI analysis spiked in the second half of last year, and that brought CadMOS management to carefully consider its options for fueling the growth that would meet such demand.

"The amount of problems with noise integrity has picked up quite unexpectedly," Huang said. "The level now is such that we were worried we could not scale up rapidly enough to meet it. And some of these customers who are not on the leading edge wanted a (lower risk entry) to signal integrity; instead of using bleeding-edge tools, they wanted the capability in the tool suites they already own."

Huang said that mainstream design moved into 0.18 micron early last year, but it is just now that much of this silicon is coming back from the fab with noise problems, or worse. He said that designers have so much silicon to play with at 0.18 micron, they are building very large chips. That ratchets up the likelihood that the silicon won't work as expected.

So, where last spring CadMOS was evaluating and turning down merger overtures, by the end of the year management could see that a combination might be the best option.

"Last year, we burned a lot of legal expenses looking into all of these acquisition options," Huang said. But Cadence could offer market access that most other suitors could not, and Jim McCanny, vice president of business development at CadMOS, said that's the reason he sees for not just this deal, but the others EDA is suddenly witnessing.

"There's a general bandwidth problem in terms of finding a channel for these great technologies we've developed," McCanny said. "We really wanted to get our technology out to the market faster."

Mentor Graphics said it is acquiring seven-person start-up SpeedGate Inc. of Austin. Tom Feist, vice president of marketing for the Exemplar Logic subsidiary of Mentor, said the Mentor HDL division will take up Speedgate's ASIC partitioning and FPGA assignment capabilities and incorporate those into its own Exemplar FPGA synthesis and Renoir design management.

The two firms have already begun working together, so early access to this technology will be given during the first quarter of 2001, with a complete rollout after that. Though a decision hasn't been made, Feist expects that the SpeedGate architecture won't be open to Mentor HDL competitor Synplicity Inc.

Financial terms of both deals aren't being disclosed; both are expected to close during the current quarter.