Xilinx Rolls Tech for SDR

Electronic News, July 23, 2001 by Gale Morrison

PLD maker ready with FEC, DSP algorithms

San Jose-based Xilinx Inc. is looking to capture mind share with wireless communications companies thinking seriously about implementing software-defined radio (SDR). To that end, today the company is releasing a wealth of DSP intellectual property (IP) cores and third-party development tools for its top-of-the-line Virtex-II FPGAs.

PLD makers, like all semiconductor suppliers, are having to gather up and offer to customers ever-increasing amounts of system expertise and engineering. This is nowhere more true than the communications space as an unprecedented amount of experimentation and exploration goes on to bring, at an acceptable cost, higher bandwidth and wider coverage to the wired and wireless infrastructure.

Enter SDR: Per Holmberg, a senior marketing manager in Xilinx's IP Solutions division, has been working with Xilinx's customers designing 3G and even 4G wireless base stations. Holmberg is seeing these client companies, which he can't publicly name yet, starting to embrace SDR. A few things have happened to bring that about, he said.

"Companies (such as Lucent Technologies Inc. and Harris Corp.) have been talking about SDR for some time, mainly in military applications because it's very expensive," Holmberg said. "Now, the technology is commercially available."

Texas Instruments Inc. and Analog Devices Inc., to name names, have made components available for the conversion of gigahertz RF signals direct to single-digit megahertz baseband frequencies, he said.

"That means your entire radio transceiver can be digital and programmable and so reconfigurable," Holmberg said. And if the baseband DSP is implemented on a Xilinx Virtex-II, the system can accomplish billions of multiply and accumulate (MAC) functions per second by lining up as many as 256 MAC units. That means performance greater than any stand-alone DSP, Holmberg said, with the huge benefit of configurability in the field for changing communications standards and changing network requirements.

"Everyone has been talking about this as a dream, more or less, but now you can do it," Holmberg said.

Catching wireless system designers now at the very start of a possibly five- to seven-year SDR deployment time is critical in convincing them to use FPGA-based DSP functionality, Holmberg said, but Xilinx (nasdaq: XLNX) is committed.

"This is a major effort that goes across all of our product lines--Virtex-II, IP, design services," he said.

Holmberg said Xilinx does not contend that the Xtreme DSPs in Virtex-II will replace other DSPs. Rather, the two types of implementation will coexist.

Today marks the first day Xilinx is offering the forward error correction (FEC) algorithms and third-party development boards for SDR applications. The initial release includes seven ready-to-use LogiCORE algorithms for FEC that detect and correct errors in wired and wireless communication systems. The LogiCORE algorithms include an enhanced Reed-Solomon encoder/decoder, a convolutional encoder, a Viterbi decoder, a Turbo convolutional code encoder/decoder and an interleaver/deinterleaver.

Several FEC cores are also available from third-party partners through the Xilinx AllianceCORE program, including a DVB-RCS turbo decoder from iCoding Technology Inc., a 3G Partnerships Program (3GPP) turbo decoder from SysOnChip Inc., and a Reed-Solomon decoder and 3GPP turbo encoder/decoder from Tilab. The cores are available immediately and downloadable from Xilinx's Web site. Pricing ranges from $5,000 to $30,000.