A Superhero of a Dilemma

Electronic News, July 23, 2001 by Richard Ball

Do FPGA makers put a bit of an FPGA into an ASIC, or does one put a bit of an ASIC into an FPGA?

Batman's pants, and Superman's for that matter, are worn on the outside. But Spiderman likes to be a regular guy-no pant posturing for him. The underwear dilemma facing your average superhero is similar to that faced by FPGA makers: Does one wrap a bit of an FPGA in an ASIC, or put a bit of an ASIC in an FPGA? Pants inside or outside?

Putting an ASIC into an FPGA, or adding hardwired logic to a programmable array, has recently become a popular move, evidenced by announcements from the big two-Altera Corp. and Xilinx Inc., both based in San Jose. However, this type of product was pioneered by much smaller companies. One of the first companies to take a stance was QuickLogic Corp. Presumably the company decided it needed to provide something different in order to distinguish itself from the swarm of second-division FPGA suppliers.

QuickLogic (nasdaq: QUIK) isn't messing about with a couple of hard intellectual property (IP) blocks-it bet the whole company on the technology. Fortunately its move seems to be paying off with revenues growing 34 percent last year to reach $53 million.

Since 1998, the company has come out with six product families in its embedded standard products range. Hard IP blocks in the families range from the relatively common- RAM or a PCI bus core-to the complex-a Fibre Channel controller or MIPS processor.

"We have a very good interconnect that allows these cores to couple to the FPGA," said Owen Bateman, European sales manager for Sunnyvale, Calif.-based QuickLogic. An anti-fuse-type connection offers faster links between metal lines than SRAM-based FPGA.

Adding a 32-bit processor is also an option with Altera (nasdaq; ALTR) in its Excalibur familly, although it offers a wider range than QuickLogic with ARM, MIPS and is negotiating with Motorola Inc. for PowerPC. Excalibur adds a stripe of hardwired processor, memory and other peripherals to an otherwise standard FPGA.

"Excalibur is part of our system-on-programmable-chip initiative, and that is basically our answer to system-on-a-chip (SOC)," said Paul Hollingworth, marketing director at Altera. "We don't think SOC works because the barriers to entry are too high."

Nonrecurring engineering costs can hit $1 million and minimum-order quantities exceed tens of thousands. "Those numbers just don't work for the majority of designs," Holling-worth added.

Hard IP inside the FPGA runs several times faster than a soft core. The ARM922 and MIPS 4Kc cores are both expected to hit 200MHz. A soft core would typically reach 50MHz. Agere Systems Inc. is that rare kind of superhero who wears quantum pants - sometimes on the inside, sometimes on the outside. The company has a range of field-programmable system chips (FPSCs), which add communications-specific cores to FPGAs but also can embed an FPGA within an ASIC.

When should a designer choose one technique over another?

"You put an FPGA in an ASIC where there are evolving standards," said Nathaniel Grier, senior manager for network communications at Agere (nasdaq: AGR/A). "The opposite occurs if there is a strict time-to-market issue."

If the latter is the case, as it almost always is, then an FPGA with a hardware-specific block can be a lifesaver. Allentown, Pa.-based Agere's FPSCs add blocks such as PCI-bus and high-speed serial communications to their FPGA architecture.

"As systems became more complex, with higher backplane rates, it became clear parallel interfaces were running out of steam," Grier said. FPSCs from the company now have interfaces running at up to 850Mbit/sec., while later this year the devices will reach 2.5 Gbit/sec. per channel. Agere is also looking at cores for Infini-band, framers and forward error correction.

Meanwhile, Actel Corp. is working its hard IP strategy along similar lines to some of Quick-Logic's and Agere's products, adding high-speed communications interfaces to its FPGAs. Its Bridge FPGAs embed the physical layer, serial/deserializer blocks, PLLs and even the protocol layer for common interface standards. The FPGA block next to this hardware remains the bulk of the die area.

In order to integrate this technology, Actel (nasdaq: ACTL) has a deal with Tality Corp. to supply the designs. This year Bridge chips will run serial links at just under lGbit/sec., and next year at 3.l25Gbit/sec. per pin. The company is wary of moving too quickly into other hard IP such as microprocessors.

"We've been looking at processors for awhile. We steer shy of processors because they are a religion to customers," said Andy Biddle, senior strategic marketing manager for Sunnyvale-based Actel.

To keep everyone happy, an FPGA supplier would need a massive family of different devices, or would have to limit itself to a narrow market. Biddle added, "And what is the benefit to a discrete processor?" Even hardwired into the FPGA, it cannot compete on price terms with the discrete option, he said. And huge support would be required in terms of design tools and compilers.