Packaging Buzz Fills Semicon

Electronic News, July 23, 2001 by Bernard Levine

Wafer-level and flip-chip among hot topics at industry trade show

SAN JOSE--The latest buzz on wafer-level, flip-chip, BGAs, chip-scale, lead-free and other hot packaging and assembly product development areas was scrutinized at last week's Semicon West here.

Wafer-level-packaging strategies were the subject of numerous technical forums and workshops.

"People are looking at wafer-level for potential cost reduction," said Craig Mitchell, vice president of the memory business unit at Tessera Technologies Inc., San Jose. However, "there are many issues, including lack of infrastructure. Also, people are looking for the killer applications for wafer-level," he said.

"Wafer-level still has a lot of difficulty," according to Joe Fjelstad of high-end design house Pacific Consultants LLC, Mountain View, Calif. Many industry researchers here examined the latest R&D to help resolve them.

Flip-chip was also a hot topic here. Flip-chip packaging is specifically targeted at high-frequency and high-demand performance marketplaces such as chipsets and telecommunications, including the integration of fiber optics and electronics, according to Patrick McKinney, senior vice president of corporate marketing at Amkor Technology Inc., Chandler, Ariz.

At Semicon, Amkor (nasdaq: AMKR) featured its Extremely Thin Chip-Scale Package (ETCSP), a 0.5mm package for use in telecom and moving media storage, he said.

"You can use this package in a stacked configuration. Additionally, we are showing our Micro Leadframe package, a near-CSP lead-frame package manufactured in a very high-density configuration that lends itself to very cost-effective manufacturing. We are showing representations of laminate packaging, which includes all our BGA packaging. We are showing flip-chip packaging capabilities both on laminates and lead-frame."

Fujitsu Microelectronics Inc. (FMI) said it had delivered the first copper interconnect flip-BGA (FCBGA) package for Altera Corp.'s PLDs. The flip-chip technology from Fujitsu is claimed to offer significant advantages in package performance for Altera's APEX 20KE, APEX 20C, APEX II and Mercury devices as well as for the Excalibur embedded processor solution. The technology improves device performance by enabling better overall thermal stress management and reducing I/O inductance.

Tessera Technololgies featured a wire-bonded micro-BGA solution complementary to its lead-bonded micro-BGA, according to Mitchell.

Flip Chip Technologies, Phoenix, is heavily involved in low-k and copper interconnect and polymer alternatives to current interconnect solutions, said Gil Olachea, president of the division of Kulicke & Soffa Industries Inc. (K&S), Willow Grove, Pa.

The K&S (nasdaq: KLIC) division also has qualified ultra-low alpha and lead-free solder alloys for flip-chip bump fabrication.

Many lead-free products were on display here from numerous companies.

ESEC of Switzerland and dmc2 of Germany noted they have cooperated to introduce a lead-free soft-solder die-attach process for power semiconductor packaging.

Also here, ESEC launched its new Flip Chip Bonder Micron 5003. It is the company's versatile platform for high-volume flip-chip and multichip modules. The company's successor to the Micron 2 features optimized cost of ownership and increased productivity due to a new vision concept. The new vision on the fly reduces the pick-and-place cycle time drastically by transforming a serial pick and view into a parallel vision process. The upward looking Line-Scan-Camera shuttles underneath the bond heads and shoots a picture of the die while the heads move at full speed from the die pick to the die place location, ESEC said.

The Package

Opto Focus

THE MICROELECTRONICS MARKETING RESEARCH COUNCIL'S FALL meeting will focus on optoelectronics packaging, covering relevant, issues, enabling technology and government policy considerations. Sponsored by the International Microelectronics and Packaging Society (IMAPS), the meeting is Oct. 5-7 at the Westin Fairfax Hotel in Washington, D.C. Program chair is E. Jan Vardaman, president of TechSearch International Inc. For info, visit www.imaps.org or contact IMAPS at 611 2nd Street, NE, Washington, D.C. 20002, Phone: 202-548-4001; Fax: 202-548-6115.

Space Talk

DONNA SIHRLEY, FORMER, MANAGER OF NASA'S MARS Exploration Program, will deliver the keynote presentation at IPC SMEMA Council's Electronics Assembly Process Exhibition and Conference, at the San Diego Convention Center, Jan. 22-24, 2002.