Is Design-for-Test Finally Coming of Age?

Electronic News, August 16, 1999 by Jon Turino

Sunnyvale, Calif.

While design-for-test (DFT) is still somewhat of a stepchild in the design engineering world, things are changing rapidly for the better. With test development times now sometimes exceeding chip design times, engineering managers have begun to realize the absolute need for BIST, boundary scan and full-scan synthesis; the time-to-market advantages of using advanced ATPG tools for achieving compact; high fault coverage tests; and the value of fault simulation to insure high product quality.

When chips were small, the silicon overhead involved in including DFT and built-in self-test (BIST) structures was often prohibitive, amounting to as much as 10 to 15 percent of overall die real estate. However, with ever-shrinking chip geometries and ever-increasing transistor counts, the overhead penalty for DFT and BIST has shrunk to the order of one to three percent, significantly reducing the barriers to inclusion. And in the deep submicron world, where interconnect delays often swamp gate delays, the performance penalty for scannable flip-flops and the occasional multiplexer for enhanced controllability and observability has been reduced to an absolute minimum.

With the inclusion of embedded memories and reusable cores from third-party semiconductor intellectual property (SIP) vendors on chips that routinely exceed a million gates, test development has become an increasingly critical factor in time-to-market. A factor that can only be mitigated by the inclusion of DFT and BIST structures that, preferably, can be automatically synthesized into a design via EDA tools designed specifically for that purpose. Today's tools can, in fact, synthesize BIST for memories, logic and cores, and can automatically generate the test patterns needed to take advantage of these structures. They can also synthesize full-scan or partial-scan logic into the functional circuit design and perform high-fault coverage, compact test pattern set generation on the resulting testable circuit. Moreover, they can do so in a much shorter time than could ever be achieved with the old manual methods.

Given the above, why is the market for DFT and BIST tools still only a small fraction of the total EDA market? Perhaps part of the answer lies in the still-pervasive division of labor between the design and test engineering functions in many organizations, and to a large extent, on the management view that test is a necessary - and expensive - evil, rather than a process monitoring and improvement step that can be leveraged for continuous production process and yield improvements.

Perhaps another part of the answer is that the large EDA suppliers haven't really paid as much attention to the development of DFT, BIST, ATPG, and fault simulation tools as they have to things like synthesis, physical layout, parametric extraction, interconnect analysis and the like. EDA vendors have also not paid enough attention to seamless integration of test-related tools into a complete design flow.

Perhaps a third part of the answer is that, until now, design teams were able to overcome design-for-test problems with brute force, making the need for test-related tools appear less urgent than the need for synthesis and place-and-route tools that can deal with deep submicron designs.

Whatever the reason, the situation is clearly changing, and the need for tools to help with DFT and BIST synthesis, ATPG and fault simulation is bubbling nearer the top of what concerns design engineering and corporate managers. It is finally becoming clear to an ever-expanding portion of the development and management community that, no matter how fast and feature-packed a new chip design is, they simply can't ship it unless they know - with a high degree of certainty - that it performs properly. And taking months to gain that degree of certainty can mean missing market windows entirely.

Predictions were made by many, including this author, that DFT would come of age in the 1980s. Then again in the 1990s. It seems like many of us were off by a decade or two. But with today and tomorrow's designs speeding relentlessly toward complexity with no relief in sight, it is probably now safe to say that DFT will come of age in the 21st century.

Jon Turino is director of marketing and business development at SynTest Technologies Inc., located in Sunnyvale, Calif.