Xilinx Talks Up 10G Ethernet

Electronic News, August 13, 2001 by Gale Morrison

Programmable logic vendor looks to head off rival Altera at I/O pass

Just three weeks after an announced end to their eight-year patent battle, programmable logic vendors Xilinx Inc. and Altera Corp. continue to make it clear that their battle for customers is far from over.

Last Tuesday, while Altera (nasdaq: ALTR) of San Jose held its High-Speed I/O Forum, rival Xilinx (nasdaq: XLNX), also of San Jose, was out shaking the trees so system interface design engineers would not forget what it has been pulling together in the same space for almost a year.

Both companies have been watching as their customers in the PC and server segments as well as in data networking have been grappling with dozens of competing proposals for a faster I/O. Perhaps never in the history of the semiconductor industry have there been so many engineering teams going in so many different directions to bring about a faster I/O, and Xilinx and Altera have tapped into that.

Earlier this summer, Altera came out with a software bridge called Atlantic that it hopes customers will use to bring together different communications protocols. Xilinx is looking to convince customers that this approach is the wrong one and that they should come to it for real expertise in system I/O in the gigabit-per-second realm.

"We are not coming up with some new standard (Altera's Atlantic) to try to confuse matters," said Babak Hedayati, senior director of product solutions marketing at Xilinx. "We detected the trend (of next-generation I/O exploration) last year, and we proposed a roadmap for it. And then we actually started delivering the IP for customers to get started ... Everyone else is kind of just turning on to this from an FPGA industry standpoint," he said.

Xilinx believes customers just Want the relevant intellectual property (IP). To that end, the company today is announcing a suite of cores for its Virtex-IIFPG As for the 10 Gigabit Ethernet market and the convergence of LANs and WANs. The suite includes a 10 Gigabit Ethernet MAC core, a 100MHZ version of the Xilinx Real PCI-X core and a CSIX interface reference design. In addition, the company has signed an agreement with API NetWorks Inc. of Concord, Mass., to license a HyperTransport core.

That is in addition to the already released RapidIO, POS-PHY L3/L4 and FlexBus4 cores from Xilinx, Hedayati said. For its part, Altera said Atlantic also supports customers working with these interfaces because it can bridge them all.

But Hedayati wants to bat down that notion.

"It's either you are shipping (the IP), or you are making up stories," he said.

The two do seem to be in agreement on one thing, albeit unintentionally. Winnowing down the number of I/O protocols is something they expect customers to do, as Altera said weeks ago and Xilinx's Hedayati also implied.

"We were at the Platform conference a couple of weeks ago, and people were talking about HyperTransport, and we were doing RapidIO," Hedayati said. "Customers were jumping up and saying, 'You've got to tell me which is the right solution.' And the answer is it's going to take a long time to figure that out. There is an abundance of various interfaces already developed or in the process of becoming a standard, and it's going to take a long time before one or a few of those develop as a de facto standard.

"What's important for those designers is to get going and to design their systems now using flexible solutions like FPGAs," he said.

Hedayati's comments bring to light the source of Xilinx and Altera's ambivalence. The greater the number of I/O schemes, the greater the need for programmable logic.