Common database not sufficient - Comment - integrated tools for integrated circuit design - Column

Electronic News, August 12, 2002 by Robert P. Smith

OVER THE LAST 15 YEARS, the EDA industry has made various attempts to create a tightly integrated tool flow with the objective of making IC design better, faster and easier, In the mid to late 1980s, the focus was on frameworks. Frameworks were supposed to make tools more usable by integrating them through APIs, sockets or file formats tied together through a common graphical user interface (GUI).

Frameworks never delivered on their original promise, but I believe there is an attempt to reincarnate them through the OpenAccess Initiative. And, with the recent merger of Synopsys and Avant!, there's no question that the industry is still striving for an integrated flow.

In the late 1990s, deep-submicron timing-closure issues made it clear that logical and physical design could no longer be separate processes. The EDA vendors that have led the traditionally separate logical and physical design markets have taken up the integration battle cry, acquired new technology and tightened the bolts that hold their point tool solutions together. However, it may be too early for them to claim victory. The underlying architecture and technology in these flows was created in the mid-80s when deep-submicron design issues, such as wire delay and signal integrity, were almost unheard of.

As much as I agree that integration is key to making IC design better, faster and easier, I don't believe bolting point tools together will solve the problem. Integration of logical and physical design is an enormous technical challenge that cannot be solved through APIs, file-based interfaces, or even common database architectures. Such systems force designers to wait until after layout to identify timing and signal-integrity issues and then go back and fix them.

These deep-submicron design problems must be addressed throughout the flow. I believe it will become very difficult to effectively address them with a patched-together point tool system. And, as gate-counts grow, the number of design closure iterations will undoubtedly increase. That's just not acceptable.

To effectively address multimillion-gate, deep-submicron designs, a completely new architecture and approach is required. I believe that true integration is critical for the future of chip design. It is also my belief that true integration requires a single, comprehensive, logical and physical design system based on a single unified data model architecture. The single data model must reside in core memory and contain all of the design data required by each of the analysis tools and implementation engines, without requiring any conversion, importing or exporting of the data.

A common database is not sufficient. I believe it is simply too slow and cumbersome to address the many tool interactions that are required to successfully implement complex deep-submicron designs. I believe this integrated system must include analysis engines such as timing and extraction, and chip implementation engines including synthesis, placement and routing that are built to work together. Such a system would have the ability to optimize wire width, length, spacing and cell sizing throughout the flow, ensuring design closure and eliminating or minimizing iterations.

True unification of logical and physical design will change our industry. It will no longer be necessary to do post-layout analysis, find hundreds or even thousands of issues, then go back and fix them. EDA verification systems will still be used to independently validate the final design, but clock skew or slew, signal integrity, power integrity and DRC/LVS violations will be treated as software, not design defects. Traditional EDA companies offering point solutions have some significant challenges ahead.

Robert P. Smith is VP of product marketing at Magma Design Automation Inc. in Cupertino, Calif Magma's Blast family of products is based on its unified data model.